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ISP1583 hi-speed universal serial bus peripheral controller rev. 03 12 july 2004 product data 1. general description the ISP1583 is a cost-optimized and feature-optimized hi-speed universal serial bus (usb) peripheral controller. it fully complies with universal serial bus speci?cation rev. 2.0 , supporting data transfer at high-speed (480 mbit/s) and full-speed (12 mbit/s). the ISP1583 provides high-speed usb communication capacity to systems based on microcontrollers or microprocessors. it communicates with a microcontroller or microprocessor of a system through a high-speed general-purpose parallel interface. the ISP1583 supports automatic detection of hi-speed usb system operation. original usb fall-back mode allows the device to remain operational under full-speed conditions. it is designed as a generic usb peripheral controller so that it can ?t into all existing device classes, such as imaging class, mass storage devices, communication devices, printing devices and human interface devices. the ISP1583 is a low-voltage device, which supports i/o pad voltages from 1.65 v to 3.6 v. the internal generic direct memory access (dma) block allows easy integration into data streaming applications. in addition, the various con?gurations of the dma block are tailored for mass storage applications. the modular approach to implementing a usb peripheral controller allows the designer to select the optimum system microcontroller from the wide variety available. the ability to reuse existing architecture and ?rmware investments shortens the development time, eliminates risk and reduces cost. the result is fast and ef?cient development of the most cost-effective usb peripheral solution. the ISP1583 is ideally suited for many types of peripherals, such as: printers; scanners; magneto-optical, compact disc, digital video disc and zip ? drives; digital still cameras; usb-to-ethernet links; cable and dsl modems. the low power consumption during suspend mode allows easy design of equipment that is compliant to the acpi?, onnow? and usb power management requirements. the ISP1583 also incorporates features such as softconnect?, a reduced frequency crystal oscillator, and integrated termination resistors. these features allow signi?cant cost savings in system design and easy implementation of advanced usb functionality into pc peripherals.
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 2 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 2. features n complies fully with: u universal serial bus speci?cation rev. 2.0 u most device class speci?cations u acpi?, onnow? and usb power management requirements n supports data transfer at high-speed (480 mbit/s) and full-speed (12 mbit/s) n direct interface to ata/atapi peripherals; applicable only in split bus mode n high performance usb peripheral controller with integrated serial interface engine (sie), parallel interface engine (pie), fifo memory and data transceiver n automatic hi-speed usb mode detection and original usb fall-back mode n supports sharing mode n supports i/o voltage range of 1.65 v to 3.6 v n supports v bus sensing n high-speed dma interface n con?gurable direct access data path from the microprocessor to an ata device n fully autonomous and multi con?guration dma operation n 7 in endpoints, 7 out endpoints and a ?xed control in/out endpoint n integrated physical 8 kbytes of multi con?guration fifo memory n endpoints with double buffering to increase throughput and ease real-time data transfer n bus-independent interface with most microcontrollers and microprocessors n 12 mhz crystal oscillator with integrated pll for low emi n software-controlled connection to the usb bus (softconnect?) n low-power consumption in operation and power-down modes; suitable for use in bus-powered usb devices n supports session request protocol (srp) that complies with on-the-go supplement to the usb speci?cation rev. 1.0a n internal power-on and low-voltage reset circuits; also supports software reset n operation over the extended usb bus voltage range (dp, dm and v bus ) n 5 v tolerant i/o pads at 3.3 v n operating temperature range from - 40 c to +85 c n available in hvqfn64 halogen-free and lead-free package. 3. applications n personal digital assistant n mass storage device, for example: zip, magneto-optical (mo), cd and dvd drives n digital video camera n digital still camera n 3g mobile phone n mp3 player n communication device, for example: router and modem n printer
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 3 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. n scanner. 4. abbreviations dma direct memory access emi electromagnetic interference fs full-speed gdma generic dma hs high-speed mdma multiword dma mmu memory management unit mo magneto-optical nrzi non-return-to-zero inverted otg on-the-go pda personal digital assistant pid packet identi?er pie parallel interface engine pio parallel input/output pll phase-locked loop se0 single-ended zero sie serial interface engine srp session request protocol usb universal serial bus. 5. ordering information table 1: ordering information type number package name description version ISP1583bs hvqfn64 plastic thermal enhanced very thin quad ?at package; no leads; 64 terminals; body 9 9 0.85 mm sot804-1
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x philips semiconductors ISP1583 hi-speed usb peripheral controller 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 03 12 july 2004 4 of 87 6. block diagram the direction of pins dreq, dack, dior and diow is determined by bit master (dma hardware register) and bit ata_mode (dma con?g uration register). (1) pin 15 is shared by ready and iordy. (2) pin 60 is shared by mode0 and da1. (3) pin 62 is shared by bus_conf and da0. fig 1. block diagram. 004aaa268 1.5 k w 12.0 k w ISP1583 hi-speed usb transceiver reset_n rref voltage regulators power-on reset memory management unit integrated ram (8 kbytes) microcontroller interface dma interface micro- controller handler dma handler dma registers 12 mhz xtal2 xtal1 to/from usb system controller philips sie/pie softconnect int internal reset data[15:0] mode0 (2) bus_conf (3) 8 ad[7:0] dreq cs0_n v cc(3v3) digital supply 1.8 v intrq iordy (1) rpu dm dp v cc(1v8) suspend wakeup agnd dgnd cs_n eot v cc(i/o) v bus 16 otg srp module analog supply 1, 5 2 34 6 7 8 dack dior diow cs1_n da0 (3) da1 (2) da2 9 101112 21 13, 35,59 ale/a0 rw_n/ rd_n ds_n/wr_n 14 15 17 18 ready (1) 19 20 22 23 to 25, 27 to 31 26, 41, 54 32, 56 60 36 37 to 40, 42 to 53 55 58 57 60 61 15 16 62 62 63 64 mode1 34 i/o pad supply 3.3 v
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 5 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7. pinning information 7.1 pinning fig 2. pin con?guration hvqfn64 (top view). 004aaa537 mode1 dgnd ale/a0 data8 data1 data2 data3 v cc(i/o) data4 data5 data6 data7 data13 data14 ready/iordy intrq dgnd diow dior dreq dack reset_n rref eot dm dp cs_n ds_n/wr_n rw_n/rd_n cs0_n cs1_n ad0 ad1 ad2 v cc(i/o) ad3 ad4 ad5 ad6 ad7 wakeup data15 v cc(1v8) v bus 4 5 6 2 3 10 11 12 7 8 9 14 15 13 45 44 43 47 46 39 38 37 42 41 40 35 34 36 51 52 53 49 50 57 58 59 54 55 56 61 62 60 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ISP1583bs agnd xtal1 xtal2 data12 v cc(i/o) data0 bus_conf/da0 v cc(3v3) int 16 agnd 1 data11 63 64 suspend 48 data9 data10 33 n.c. v cc(1v8) 32 da2 17 rpu mode0/da1 dgnd
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 6 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.2 pin description fig 3. pin con?guration hvqfn64 (bottom view). 004aaa376 data9 data8 data7 dgnd data5 data4 v cc(i/o) data3 data2 data1 data0 ale/a0 ad6 ad5 rpu dp dm agnd rref eot reset_n dack dior dreq dgnd intrq wakeup v cc(3v3) bus_conf/da0 mode0/da1 dgnd xtal1 xtal2 v cc(1v8) v bus v cc(i/o) data15 data14 data13 data12 cs_n ad4 ad2 v cc(i/o) 13 12 11 15 14 7 6 5 10 9 8 3 2 4 36 37 38 34 35 42 43 44 39 40 41 46 47 45 30 29 28 32 31 24 23 22 27 26 25 20 19 21 63 62 61 60 59 58 57 56 55 54 53 52 51 50 ISP1583bs diow ad0 ad1 ad7 ad3 data6 rw_n/rd_n ds_n/ wr_n agnd 1 int 16 v cc(1v8) 18 17 da2 33 mode1 n.c. 48 data10 data11 49 suspend 64 ready/iordy cs0_n cs1_n gnd (exposed die pad) bottom view terminal 1 table 2: pin description symbol [1] pin type [2] description agnd 1 - analog ground rpu 2 a pull-up resistor connection; this pin must be connected to 3.3 v through an external 1.5 k w resistor for pulling-up pin dp dp 3 a usb d+ line connection (analog) dm 4 a usb d - line connection (analog) agnd 5 - analog ground rref 6 a external bias resistor connection; this pin must be connected to ground via a 12.0 k w 1 % resistor
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 7 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. reset_n 7 i reset input (500 m s); a low level produces an asynchronous reset; connect to v cc(3v3) for power-on reset (internal por circuit) ttl; 5 v tolerant [6] eot 8 i end-of-transfer input (programmable polarity); used in dma slave mode only; when not in use, connect this pin to v cc(i/o) through a 10 k w resistor input pad; ttl; 5 v tolerant [6] dreq 9 i/o dma request input or output (programmable polarity); the signal direction depends on bit master in register dma hardware (see ta b l e 5 7 ): ? input: dma master if bit master = 1 ? output: dma slave if bit master = 0. when not in use, in the default setting, this pin must be connected to ground through a 10 k w resistor. bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] dack 10 i/o dma acknowledge input or output (programmable polarity); the signal direction depends on bit master in register dma hardware (see ta b l e 5 7 ): ? input: dma slave if bit master = 0 ? output: dma master if bit master = 1. when not in use, in the default setting, this pin must be connected to v cc(i/o) through a 10 k w resistor. bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] dior 11 i/o dma read strobe input or output (programmable polarity); the signal direction depends on bit master in register dma hardware (see ta b l e 5 7 ): ? input: dma slave if bit master = 0 ? output: dma master if bit master = 1. when not in use, in the default setting, this pin must be connected to v cc(i/o) through a 10 k w resistor. bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] diow 12 i/o dma write strobe input or output (programmable polarity); the signal direction depends on bit master in register dma hardware (see ta b l e 5 7 ): ? input: dma slave if bit master = 0 ? output: dma master if bit master = 1. when not in use, in the default setting, this pin must be connected to v cc(i/o) through a 10 k w resistor. bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] dgnd 13 - digital ground intrq 14 i interrupt request input; from the ata/atapi peripheral; use a 10 k w resistor to pull-down input pad; ttl; 5 v tolerant [6] table 2: pin description continued symbol [1] pin type [2] description
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 8 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. ready/ iordy 15 i/o signal ready output used in generic processor mode: ? low: the ISP1583 is processing a previous command or data and is not ready for the next command or data transfer ? high: the ISP1583 is ready for the next microprocessor read or write. dma ready input used in split bus mode for accessing ata/atapi peripherals (pio mode only). bidirectional pad; 10 ns slew-rate control; ttl; 5 v tolerant [6] int 16 o interrupt output; programmable polarity (active high or low) and signaling (edge or level triggered) cmos output; 8 ma drive da2 [5] 17 o address output to select the task file register of an ata/atapi device; see ta b l e 5 9 cmos output; 8 ma drive cs_n 18 i chip selection input input pad; ttl; 5 v tolerant [6] rw_n/ rd_n 19 i read and write input for motorola style, this function is determined by pin mode0 = low during power-up. read input for 8051 style, this function is determined by pin mode0 = high during power-up. input pad; ttl; 5 v tolerant [6] ds_n/ wr_n 20 i data selection input for motorola style, this function is determined by pin mode0 = low at power-up. write input for 8051 style, this function is determined by pin mode0 = high at power-up. input pad; ttl; 5 v tolerant [6] cs0_n [5] 21 o chip selection output 0 for ata/atapi device; see ta bl e 5 9 cmos output; 8 ma drive cs1_n [5] 22 o chip selection output 1 for ata/atapi device; see ta bl e 5 9 cmos output; 8 ma drive ad0 23 i/o bit 0 of multiplexed address and data bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] ad1 24 i/o bit 1 of multiplexed address and data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] ad2 25 i/o bit 2 of multiplexed address and data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] v cc(i/o) [3] 26 - i/o pad supply voltage (1.65 v to 3.6 v); see section 8.15 ad3 27 i/o bit 3 of multiplexed address and data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] ad4 28 i/o bit 4 of multiplexed address and data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] ad5 29 i/o bit 5 of multiplexed address and data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] table 2: pin description continued symbol [1] pin type [2] description
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 9 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. ad6 30 i/o bit 6 of multiplexed address and data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] ad7 31 i/o bit 7 of multiplexed address and data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] v cc(1v8) [3] 32 - voltage regulator output (1.8 v 0.15 v); tapped out voltage from the internal regulator; this regulated voltage cannot drive external devices; decouple this pin using a 0.1 m f capacitor; see section 8.15 n.c. 33 - not connected mode1 34 i mode selection input 1; used in split bus mode only: ? low: ale function (address latch enable) ? high: a0 function (address/data indicator). remark: when operating in generic processor mode, set pin mode1 high. input pad; ttl; 5 v tolerant [6] dgnd 35 - digital ground ale/a0 36 i address latch enable input when pin mode1 = low during power-up, a falling edge latches the address on the multiplexed address and data bus ad[7:0]. address and data selection input when pin mode1 = high during power-up, the function is determined by the level on this pin (detected on the rising edge of the wr_n pulse): ? high: bus ad[7:0] is a register address ? low: bus ad[7:0] is register data; used in split bus mode only. remark: when operating in generic processor mode with pin mode1 = high, this pin must be pulled down using a 10 k w resistor. input pad; ttl; 5 v tolerant [6] data0 37 i/o bit 0 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] data1 38 i/o bit 1 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] data2 39 i/o bit 2 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] data3 40 i/o bit 3 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] v cc(i/o) [3] 41 - i/o pad supply voltage (1.65 v to 3.6 v); see section 8.15 data4 42 i/o bit 4 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] data5 43 i/o bit 5 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] table 2: pin description continued symbol [1] pin type [2] description
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 10 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. data6 44 i/o bit 6 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] data7 45 i/o bit 7 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] data8 46 i/o bit 8 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] data9 47 i/o bit 9 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] data10 48 i/o bit 10 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] data11 49 i/o bit 11 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] data12 50 i/o bit 12 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] data13 51 i/o bit 13 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] data14 52 i/o bit 14 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] data15 53 i/o bit 15 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant [6] v cc(i/o) [3] 54 - i/o pad supply voltage (1.65 v to 3.6 v); see section 8.15 v bus 55 a usb bus power sensing input used to detect whether the host is connected or not; when v bus is not detected, pin rpu is internally disconnected from pin dp in approximately 4 ns v bus pulsing output in otg mode. connect a 1 m f electrolytic capacitor and a 1 m w pull-down resistor to ground; see section 8.13 5 v tolerant [6] v cc(1v8) [3] 56 - voltage regulator output (1.8 v 0.15 v); tapped out voltage from the internal regulator; this regulated voltage cannot drive external devices; decouple this pin using 4.7 m f and 0.1 m f capacitors; see section 8.15 xtal2 57 o crystal oscillator output (12 mhz); connect a fundamental parallel-resonant crystal; leave this pin open when using an external clock source on pin xtal1; see ta bl e 9 9 xtal1 58 i crystal oscillator input (12 mhz); connect a fundamental parallel-resonant crystal or an external clock source (leaving pin xtal2 unconnected); see ta bl e 9 9 dgnd 59 - digital ground table 2: pin description continued symbol [1] pin type [2] description
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 11 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] symbol names ending with underscore n (for example, name_n) represent active low signals. [2] all outputs and i/o pins can source 4 ma. [3] add a decoupling capacitor (0.1 m f) to all the supply pins. for better emi results, add a 0.01 m f capacitor in parallel to the 0.1 m f. [4] the dma bus is in 3-state until a dma command (see section 9.4.1 ) is executed. [5] the control signals are not 3-state. [6] 5 v tolerant when v cc(i/o) = 3.3 v. mode0/ da1 [5] 60 i/o mode selection input 0 selects the read/write strobe functionality in generic processor mode during power-up: ? low: for motorola style; the function of pin 19 is rw_n and pin 20 is ds_n ? high: for 8051 style; the function of pin 19 is rd_n and pin 20 is wr_n. address selection output selects the task file register of an ata/atapi device during normal operation; see ta b l e 5 9 bidirectional pad; 10 ns slew-rate control; ttl; 5 v tolerant [6] v cc(3v3) [3] 61 - regulator supply voltage (3.3 v 0.3 v); this pin supplies the internal regulator; see section 8.15 bus_conf/ da0 [5] 62 i/o bus con?guration input selects bus mode during power-up at: ? low: split bus mode; multiplexed 8-bit address and data bus on ad[7:0], separate dma data bus on data[15:0] [4] ? high: generic processor mode; separate 8-bit address on ad[7:0], 16-bit processor data bus on data[15:0]. dma is multiplexed on the processor bus as data[15:0]. address selection output selects the task file register of an ata/atapi device at normal operation; see ta b l e 5 9 bidirectional pad; 10 ns slew-rate control; ttl; 5 v tolerant [6] wakeup 63 i wake-up input; when this pin is at the high level, the chip is prevented from getting into the suspend state and the chip wakes up from the suspend state; when not in use, connect this pin to ground through a 10 k w resistor input pad; ttl; 5 v tolerant [6] suspend 64 o suspend state indicator output; used as a power switch control output for powered-off application or as a resume signal to the cpu for powered-on application cmos output; 8 ma drive gnd exposed die pad ground supply; down bonded to the exposed die pad (heatsink); to be connected to the dgnd during pcb layout table 2: pin description continued symbol [1] pin type [2] description
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 12 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8. functional description the ISP1583 is a high-speed usb peripheral controller. it implements the hi-speed usb or the original usb physical layer and the packet protocol layer. it maintains up to 16 usb endpoints concurrently (control in and control out, 7 in and 7 out con?gurable) along with endpoint ep0 setup, which accesses the setup buffer. the usb chapter 9 protocol handling is executed by means of external ?rmware. the ISP1583 has a fast general-purpose interface for communication with most types of microcontrollers and microprocessors. this microcontroller interface is con?gured by pins bus_conf, mode1 and mode0 to accommodate most interface types. two bus con?gurations are available, selected via input bus_conf during power-up: ? generic processor mode (pin bus_conf = high): C ad[7:0]: 8-bit address bus (selects target register) C data[15:0]: 16-bit data bus (shared by processor and dma) C control signals: rw_n and ds_n or rd_n and wr_n (selected via pin mode0), cs_n C dma interface (generic slave mode only): uses lines data[15:0] as data bus, dior and diow as dedicated read and write strobes. ? split bus mode (pin bus_conf = low): C ad[7:0]: 8-bit local microprocessor bus (multiplexed address and data) C data[15:0]: 16-bit dma data bus C control signals: cs_n, ale or a0 (selected via pin mode1), rw_n and ds_n or rd_n and wr_n (selected via pin mode0) C dma interface (master or slave mode): uses dior and diow as dedicated read and write strobes. for high-bandwidth data transfer, the integrated dma handler can be invoked to transfer data to or from external memory or devices. the dma interface can be con?gured by writing to the proper dma registers (see section 9.4 ). the ISP1583 supports hi-speed usb and original usb signaling. the usb signaling speed is automatically detected. the ISP1583 has 8 kbytes of internal fifo memory, which is shared among the enabled usb endpoints there are 7 in endpoints, 7 out endpoints and 2 control endpoints that are a ?xed 64 bytes long. any of the 7 in and 7 out endpoints can be separately enabled or disabled. the endpoint type (interrupt, isochronous or bulk) and packet size of these endpoints can be individually con?gured depending on the requirements of the application. optional double buffering increases the data throughput of these data endpoints. the ISP1583 requires 3.3 v power supply. it has 5 v tolerant i/o pads when operating at v cc(i/o) = 3.3 v and an internal 1.8 v regulator for powering the analog transceiver. the i/o voltage can range from 1.65 v to 3.6 v.
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 13 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. the ISP1583 operates on a 12 mhz crystal oscillator. an integrated 40 pll clock multiplier generates the internal sampling clock of 480 mhz. 8.1 dma interface, dma handler and dma registers the dma block can be subdivided into two blocks: dma handler and dma interface. the ?rmware writes to the dma command register to start a dma transfer (see ta b l e 4 9 ). the command opcode determines whether a generic dma, parallel i/o (pio) or multiword dma (mdma) transfer will start. the handler interfaces to the same fifo (internal ram) as used by the usb core. on receiving the dma command, the dma handler directs the data from the endpoint fifo to the external dma device or from the external dma device to the endpoint fifo. the dma interface con?gures the timing and the dma handshake. data can be transferred using either the dior and diow strobes or by the dack and dreq handshakes. the dma con?gurations are set up by writing to the dma con?guration register (see ta b l e 5 4 and ta b l e 5 5 ). for an ide-based storage interface, applicable dma modes are pio and mdma (multiword dma; ata). for a generic dma interface, dma modes that can be used are generic dma (gdma) slave. remark: the dma endpoint buffer length must be a multiple of 4 bytes. for details on dma registers, see section 9.4 . 8.2 hi-speed usb transceiver the analog transceiver directly interfaces to the usb cable through integrated termination resistors. the high-speed transceiver requires an external resistor (12.0 k w 1 %) between pin rref and ground to ensure an accurate current mirror that generates the hi-speed usb current drive. a full-speed transceiver is integrated as well. this makes the ISP1583 compliant to hi-speed usb and original usb, supporting both the high-speed and full-speed physical layers. after automatic speed detection, the philips serial interface engine (sie) sets the transceiver to use either high-speed or full-speed signaling. 8.3 mmu and integrated ram the memory management unit (mmu) and the integrated ram provide the conversion between the usb speed (full-speed: 12 mbit/s; high-speed: 480 mbit/s) and the microcontroller handler or the dma handler. the data from the usb bus is stored in the integrated ram, which is cleared only when the microcontroller has read or written all data from or to the corresponding endpoint buffer or when the dma handler has read or written all data from or to the endpoint buffer. the out endpoint buffer can also be cleared forcibly by setting bit clbuf in the control function register. a total of 8 kbytes ram is available for buffering.
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 14 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.4 microcontroller interface and microcontroller handler the microcontroller interface allows direct interfacing to most microcontrollers and microprocessors. the interface is con?gured at power-up through pins bus_conf, mode1 and mode0. when pin bus_conf = high, the microcontroller interface switches to generic processor mode in which ad[7:0] is the 8-bit address bus and data[15:0] is the separate 16-bit data bus. if pin bus_conf = low, the interface is in split bus mode , where ad[7:0] is the local microprocessor bus (multiplexed address and data) and data[15:0] is solely used as the dma bus. when pin mode0 = high, pins rd_n and wr_n are the read and write strobes (8051 style). if pin mode0 = low, pins rw_n and ds_n pins represent the direction and data strobe (motorola style). when pin mode1 = low, pin ale is used to latch the multiplexed address on pins ad[7:0]. when pin mode1 = high, pin a0 is used to indicate address or data. pin mode1 is only used in split bus mode; in generic processor mode it must be tied to v cc(i/o) . the microcontroller handler allows the external microcontroller to access the register set in the philips sie as well as the dma handler. the initialization of the dma con?guration is done through the microcontroller handler. 8.5 otg srp module the otg supplement de?nes a session request protocol (srp), which allows a b-device to request the a-device to turn on v bus and start a session. this protocol allows the a-device, which may be battery-powered, to conserve power by turning off v bus when there is no bus activity while still providing a means for the b-device to initiate bus activity. any a-device, including a pc or laptop, can respond to srp. any b-device, including a standard usb peripheral, can initiate srp. the ISP1583 is a device that can initiate srp. 8.6 philips high-speed transceiver 8.6.1 philips parallel interface engine (pie) in the high-speed (hs) transceiver, the philips pie interface uses a 16-bit parallel bidirectional data interface. the functions of the hs module also include bit-stuf?ng or destuf?ng and non-return-to-zero inverted (nrzi) encoding or decoding logic. 8.6.2 peripheral circuit to maintain a constant current driver for hs transmit circuits and to bias other analog circuits, an internal band gap reference circuit and an rref resistor form the reference current. this circuit requires an external precision resistor (12.0 k w 1%) connected to the analog ground.
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 15 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.6.3 hs detection the ISP1583 handles more than one electrical statefull-speed (fs) or high-speed (hs)under the usb speci?cation. when the usb cable is connected from the peripheral to the host controller, the ISP1583 defaults to the fs state until it sees a bus reset from the host controller. during the bus reset, the peripheral initiates an hs chirp to detect whether the host controller supports hi-speed usb or original usb. chirping must be done with the pull-up resistor connected and the internal termination resistors disabled. if the hs handshake shows that there is an hs host connected, then the ISP1583 switches to the hs state. in the hs state, the ISP1583 should observe the bus for periodic activity. if the bus remains inactive for 3 ms, the peripheral switches to the fs state to check for a single-ended zero (se0) condition on the usb bus. if an se0 condition is detected for the designated time (100 m s to 875 m s; refer to section 7.1.7.6 of the usb speci?cation rev. 2.0), the ISP1583 switches to the hs chirp state to perform an hs detection handshake. otherwise, the ISP1583 remains in the fs state adhering to the bus-suspend speci?cation. 8.7 philips serial interface engine (sie) the philips sie implements the full usb protocol layer. it is completely hardwired for speed and needs no ?rmware intervention. the functions of this block include: synchronization pattern recognition, parallel or serial conversion, bit-stuf?ng or destuf?ng, crc checking or generation, packet identi?er (pid) veri?cation or generation, address recognition, handshake evaluation or generation. 8.8 softconnect the connection to the usb is established by pulling pin dp (for full-speed devices) high through a 1.5 k w pull-up resistor. in the ISP1583, an external 1.5 k w pull-up resistor must be connected between pin rpu and 3.3 v. the rpu pin connects the pull-up resistor to pin dp, when bit softct in the mode register is set (see ta b l e 2 1 and ta b l e 2 2 ). after a hardware reset, the pull-up resistor is disconnected by default (bit softct = 0). the usb bus reset does not change the value of bit softct. when the v bus is not present, the softct bit must be set to logic 0 to comply with the back-drive voltage. 8.9 system controller the system controller implements the usb power-down capabilities of the ISP1583. registers are protected against data corruption during wake-up following a resume (from the suspend state) by locking the write access until an unlock code has been written in the unlock device register (see ta b l e 8 9 and ta b l e 9 0 ). 8.10 modes of operation the ISP1583 has two bus con?guration modes, selected via pin bus_conf at power-up:
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 16 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? split bus mode (bus_conf = low): 8-bit multiplexed address and data bus, and separate 8-bit and 16-bit dma bus ? generic processor mode (bus_conf = high): separate 8-bit address and 16-bit data bus. details of the bus con?gurations for each mode are given in ta b l e 3 . typical interface circuits for each mode are given in section 14 . 8.11 output pins status ta b l e 4 illustrates the behavior of output pins when v cc(i/o) is supplied with v cc(3v3) in various operating conditions. [1] x: dont care. [2] dead: the usb cable is plugged-out and v cc(i/o) is not available. [3] plug-out: the usb cable is not present but v cc(i/o) is available. [4] plug-in: the usb cable is being plugged-in and v cc(i/o) is available. 8.12 interrupt 8.12.1 interrupt output pin the interrupt con?guration register of the ISP1583 controls the behavior of the int output pin. the polarity and signaling mode of the int pin can be programmed by setting bits intpol and intlvl of the interrupt con?guration register (r/w: 10h); see ta b l e 2 5 . bit glintena of the mode register (r/w: och) is used to enable table 3: bus con?guration modes pin bus_conf pio width dma width description width = 0 width = 1 low ad[7:0] d[7:0] d[15:0] split bus mode: ? multiplexed address/data on pins ad[7:0] ? separate 8- bit or 16-bit dma bus on pins data[15:0]. high a[7:0] and d[15:0] d[7:0] d[15:0] generic processor mode: ? separate 8-bit address on pins ad[7:0] ? 16-bit data (pio and dma) on pins data[15:0]. table 4: ISP1583 pin status [1] v cc(3v3) v cc(i/o) state pin reset_n int_n suspend data[15:0] dreq da2 da1 da0 cs0_n 0 v 0 v dead [2] xxx x xxxxx 0 v 1.65 v to 3.6 v plug-out [3] x low high input high-z high input input high 0v -> 3.3 v 1.65 v to 3.6 v plug-in [4] x low high high-z high-z high input input high 3.3 v 1.65 v to 3.6 v reset low high low high-z high-z high high high high 3.3 v 1.65 v to 3.6 v normal high high low high-z high-z high high high high
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 17 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. pin int; see ta b l e 2 2 . default settings after reset are active low and level mode. when pulse mode is selected, a pulse of 60 ns is generated when the or-ed combination of all interrupt bits changes from logic 0 to logic 1. figure 4 shows the relationship between the interrupt events and pin int. each of the indicated usb and dma events is logged in a status bit of the interrupt register and the dma interrupt reason register, respectively. corresponding bits in the interrupt enable register and the dma interrupt enable register determine whether or not an event will generate an interrupt. interrupts can be masked globally by means of bit glintena of the mode register. field cdbgmod[1:0] of the interrupt con?guration register controls the generation of the int signals for the control pipe. field ddbgmodin[1:0] of the interrupt con?guration register controls the generation of the int signals for the in pipe. field ddbgmodout[1:0] of the interrupt con?guration register controls the generation of the int signals for the out pipe; see ta b l e 2 6 . 8.12.2 interrupt control bit glintena in the mode register is a global enable/disable bit. the behavior of this bit is given in figure 5 . event a: when an interrupt event occurs (for example, sof interrupt) with bit glintena set to logic 0, an interrupt will not be generated at pin int. it will, however, be registered in the corresponding interrupt register bit. event b: when bit glintena is set to logic 1, pin int is asserted because bit sof in the interrupt register is already set. event c: if the ?rmware sets bit glintena to logic 0, pin int will still be asserted. the bold dashed line shows the desired behavior of pin int. deassertion of pin int can be achieved either by clearing all the interrupt register or the dma interrupt reason register, depending on the event. remark: when clearing an interrupt event, perform write to all the bytes of the register. for more information on interrupt control, see section 9.2.2 , section 9.2.5 and section 9.5.1 .
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors ISP1583 hi-speed usb peripheral controller 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 03 12 july 2004 18 of 87 fig 4. interrupt logic. bsy_done or interrupt register dma interrupt reason register dma interrupt enable register interrupt enable register tf_rd_done cmd_intrq_ok gdma_stop ext_eot int_eot ie_bsy_done ie_tf_rd_done ie_cmd_intrq_ok ie_gdma_stop ie_ext_eot ie_int_eot ...... ...... ...... .............. or iebrst iesof iedma iep7rx iep7tx breset sof dma ep7rx ep7tx ...... .... ...... .... ...... .... 004aaa267 latch glintena intpol le interrupt configuration register mode register int pulse or level generator
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 19 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.13 v bus sensing the v bus pin is one of the ways to wake up the clock when the ISP1583 is suspended with bit clkaon set to logic 0 (clock off option). to detect whether the host is connected or not, that is v bus sensing, a 1 m w resistor and a 1 m f electrolytic capacitor must be added to damp the overshoot upon plug-in. pin int: high = deassert; low = assert (individual interrupts are enabled). fig 5. behavior of bit glintena. int pin 004aaa394 glintena = 0 sof asserted glintena = 1 sof asserted glintena = 0 (during this time, an interrupt event occurs. for example, sof asserted.) a b c fig 6. resistor and electrolytic capacitor needed for v bus sensing. fig 7. oscilloscope reading: no resistor and capacitor in the network. fig 8. oscilloscope reading: with resistor and capacitor in the network. 1 m w ISP1583 004aaa449 + 1 f 55 usb connector 004aaa441 004aaa442
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 20 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.14 power-on reset the ISP1583 requires a minimum pulse width of 500 m s. the reset_n pin can be either connected to v cc(3v3) (using the internal por circuit) or externally controlled (by the microcontroller, asic, and so on). when v cc(3v3) is directly connected to the reset_n pin, the internal pulse width t porp will be typically 200 ns. the power-on reset function can be explained by viewing the dips at t2-t3 and t4-t5 on the v cc(por) curve ( figure 9 ). t0 the internal por starts with a high level. t1 the detector will see the passing of the trip level and a delay element will add another t porp before it drops to low. t2-t3 the internal por pulse will be generated whenever v cc(por) drops below v trip for more than 11 m s. t4-t5 the dip is too short (< 11 m s) and the internal por pulse will not react and will remain low. figure 10 shows the availability of the clock with respect to the external por. 8.15 power supply the ISP1583 can be powered by 3.3 v 0.3 v, and from 1.65 v to 3.6 v at the interface. for connection details, see figure 11 . (1) porp = power-on reset pulse. fig 9. por timing. stable external clock is to be available at a. fig 10. clock with respect to the external por. 004aaa389 v bat(por) t0 t1 t2 t3 t4 t5 v trip t porp porp (1) t porp por external clock a 004aaa365
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 21 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. if the ISP1583 is powered by v cc(3v3) = 3.3 v, an integrated 3.3 v-to-1.8 v voltage regulator provides a 1.8 v supply voltage for the internal logic. in sharing mode (that is, when v cc(3.3) is not present and v cc(i/o) is present), all the i/o pins are in 3-state, the interrupt pin is connected to ground, and the suspend pin is connected to v cc(i/o) . see ta b l e 4 . ta b l e 5 shows power modes in which the ISP1583 can be operated. [1] the power supply to the ic (v cc(3v3) ) is 3.3 v. therefore, if the application is bus-powered, a 3.3 v regulator needs to be used. [2] v cc(i/o) can range from 1.65 v to 3.6 v. if the application is bus-powered, a voltage regulator needs to be used. (1) it is mandatory to use a 4.7 m f electrolytic capacitor on pin 56. fig 11. ISP1583 with 3.3 v supply. table 5: power modes v cc(3v3) v cc(i/o) power mode v bus [1] v bus [2] bus-powered self-powered self-powered self-powered v bus [1] self-powered power-sharing (hybrid) 004aaa271 61 v cc(i/o) ISP1583 3.3 v 0. 3 v v cc(i/o) v cc(3v3) 26 41 v cc(i/o) v cc(1v8) 54 56 4.7 f (1) 0.1 f 0.01 f 0.1 f 0.01 f 0.1 f 1.65 v to 3.6 v 0.01 f 0.1 f 0.01 f 0.1 f v cc(1v8) 32 0.1 f +
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 22 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.15.1 power-sharing mode as can be seen in figure 12 , in power-sharing mode, v cc(3v3) is supplied by the output of the 5 v-to-3.3 v voltage regulator. the input to the regulator is from v bus . v cc(i/o) is supplied through the power source of the system. when the usb cable is plugged in, the ISP1583 goes through the power-on reset cycle. in this mode, otg is disabled. the processor will experience continuous interrupt because the default status of the interrupt pin when operating in sharing mode with the v bus not present is low. to overcome this, implement external v bus sensing circuitry. the output from the voltage regulator can be connected to pin gpio of the processor to qualify the interrupt from the ISP1583. fig 12. power-sharing mode. fig 13. interrupt pin status during power off in power-sharing mode. 004aaa458 ISP1583 + - 5 v-to-3.3 v usb voltage regulator to gpio of processor for sensing v bus 1 m w v cc(3v3) v cc(i/o) v bus rpu v bus 1 f 1.5 k w + - 004aaa459 v cc(i/o) v cc(3v3) int power off power off
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 23 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 6: operation truth table for softconnect ISP1583 operation power supply bit softct in mode register v cc(3v3) v cc(i/o) rpu (3.3 v) v bus normal bus operation 3.3 v 3.3 v 3.3 v 5 v enabled core power is lost 0 v 3.3 v 0 v 0 v not applicable table 7: operation truth table for clock off during suspend ISP1583 operation power supply clock off during suspend v cc(3v3) v cc(i/o) rpu (3.3 v) v bus clock will wake up: after a resume and after a bus reset 3.3 v 3.3 v 3.3 v 5 v enabled core power is lost 0 v 3.3 v 0 v 0 v not applicable table 8: operation truth table for back voltage compliance ISP1583 operation power supply bit softct in mode register v cc(3v3) v cc(i/o) rpu (3.3 v) v bus back voltage is not measured in this mode 3.3 v 3.3 v 3.3 v 5 v enabled back voltage is not an issue because core power is lost 0 v 3.3 v 0 v 0 v not applicable table 9: operation truth table for otg ISP1583 operation power supply otg register v cc(3v3) v cc(i/o) rpu (3.3 v) v bus srp is not applicable 3.3 v 3.3 v 3.3 v 5 v not applicable otg is not possible because v bus is not present and so core power is lost 0 v 3.3 v 0 v 0 v not applicable
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 24 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.15.2 self-powered mode in self-powered mode, v cc(3v3) and v cc(i/o) are supplied by the system. bit softct in the mode register must be always logic 1. see figure 14 . [1] when the usb cable is removed, softconnect is disabled. fig 14. self-powered mode. table 10: operation truth table for softconnect ISP1583 operation power supply bit softct in mode register v cc(3v3) v cc(i/o) rpu (3.3 v) v bus normal bus operation 3.3 v 3.3 v 3.3 v 5 v enabled no pull-up on dp 3.3 v 3.3 v 3.3 v 0 v [1] disabled table 11: operation truth table for clock off during suspend ISP1583 operation power supply clock off during suspend v cc(3v3) v cc(i/o) rpu (3.3 v) v bus clock will wake up: after a resume and after a bus reset 3.3 v 3.3 v 3.3 v 5 v enabled clock will wake up: after detecting the presence of v bus 3.3 v 3.3 v 3.3 v 0 v => 5 v enabled table 12: operation truth table for back voltage compliance ISP1583 operation power supply bit softct in mode register v cc(3v3) v cc(i/o) rpu (3.3 v) v bus back voltage is not measured in this mode 3.3 v 3.3 v 3.3 v 5 v enabled back voltage is not an issue because pull-up on dp will not be present when v bus is not present 3.3 v 3.3 v 3.3 v 0 v disabled 004aaa461 ISP1583 + - usb 1 m w v cc(3v3) v cc(i/o) v bus rpu v bus 1 f 1.5 k w + -
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 25 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.15.3 bus-powered mode in bus-powered mode (see figure 15 ), v cc(3v3) and v cc(i/o) are supplied by the output of the 5 v-to-3.3 v voltage regulator. the input to the regulator is from v bus . on plugging in of the usb cable, the ISP1583 goes through the power-on reset cycle. in this mode, otg is disabled. table 13: operation truth table for otg ISP1583 operation power supply otg register v cc(3v3) v cc(i/o) rpu (3.3 v) v bus srp is not applicable 3.3 v 3.3 v 3.3 v 5 v not applicable srp is possible 3.3 v 3.3 v 3.3 v 0 v operational fig 15. bus-powered mode. table 14: operation truth table for softconnect ISP1583 operation power supply bit softct in mode register v cc(3v3) v cc(i/o) rpu (3.3 v) v bus normal bus operation 3.3 v 3.3 v 3.3 v 5 v enabled power is lost 0 v 0 v 0 v 0 v not applicable table 15: operation truth table for clock off during suspend ISP1583 operation power supply clock off during suspend v cc(3v3) v cc(i/o) rpu (3.3 v) v bus clock will wake up: after a resume and after a bus reset 3.3 v 3.3 v 3.3 v 5 v enabled power is lost 0 v 0 v 0 v 0 v not applicable 004aaa463 ISP1583 5 v-to-3.3 v usb voltage regulator 1 m w v cc(3v3) v cc(i/o) v bus v bus 1 f rpu + - 1.5 k w
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 26 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 16: operation truth table for back voltage compliance ISP1583 operation power supply bit softct in mode register v cc(3v3) v cc(i/o) rpu (3.3 v) v bus back voltage is not measured in this mode 3.3 v 3.3 v 3.3 v 5 v enabled power is lost 0 v 0 v 0 v 0 v not applicable table 17: operation truth table for otg ISP1583 operation power supply otg register v cc(3v3) v cc(i/o) rpu (3.3 v) v bus srp is not applicable 3.3 v 3.3 v 3.3 v 5 v not applicable power is lost 0 v 0 v 0 v 0 v not applicable
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 27 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9. register description table 18: register overview name destination address description size (bytes) reference initialization registers address device 00h usb device address and enable 1 section 9.2.1 on page 29 mode device 0ch power-down options, global interrupt enable, softconnect 1 section 9.2.2 on page 29 interrupt con?guration device 10h interrupt sources, trigger mode, output polarity 1 section 9.2.3 on page 32 otg device 12h otg implementation 1 section 9.2.4 on page 32 interrupt enable device 14h interrupt source enabling 4 section 9.2.5 on page 34 data ?ow registers endpoint index endpoints 2ch endpoint selection, data ?ow direction 1 section 9.3.1 on page 36 control function endpoint 28h endpoint buffer management 1 section 9.3.2 on page 37 data port endpoint 20h data access to endpoint fifo 2 section 9.3.3 on page 38 buffer length endpoint 1ch packet size counter 2 section 9.3.4 on page 39 buffer status endpoint 1eh buffer status for each endpoint 1 section 9.3.5 on page 40 endpoint maxpacketsize endpoint 04h maximum packet size 2 section 9.3.6 on page 41 endpoint type endpoint 08h selects endpoint type: control, isochronous, bulk or interrupt 2 section 9.3.7 on page 42 dma registers dma command dma controller 30h controls all dma transfers 1 section 9.4.1 on page 44 dma transfer counter dma controller 34h sets byte count for dma transfer 4 section 9.4.2 on page 46 dma con?guration dma controller 38h byte 0: sets gdma con?guration (counter enable, burst length, data strobing, bus width) 1 section 9.4.3 on page 47 39h byte 1: sets ata con?guration (iordy enable, mode selection: ata/mdma/pio) 1 dma hardware dma controller 3ch endian type, master or slave selection, signal polarity for dack, dreq, diow, dior 1 section 9.4.4 on page 49
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 28 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.1 register access register access depends on the bus width used: ? 8-bit bus: multi-byte registers are accessed lower byte (lsbyte) ?rst ? 16-bit bus: for single-byte registers, the upper byte (msbyte) must be ignored. endpoint speci?c registers are indexed via the endpoint index register. the target endpoint must be selected before accessing the following registers: task file 1f0 atapi peripheral 40h single address word register: byte 0 (lower byte) is accessed ?rst 2 section 9.4.5 on page 50 task file 1f1 atapi peripheral 48h ide device access 1 task file 1f2 atapi peripheral 49h ide device access 1 task file 1f3 atapi peripheral 4ah ide device access 1 task file 1f4 atapi peripheral 4bh ide device access 1 task file 1f5 atapi peripheral 4ch ide device access 1 task file 1f6 atapi peripheral 4dh ide device access 1 task file 1f7 atapi peripheral 44h ide device access (write only; reading returns ffh) 1 task file 3f6 atapi peripheral 4eh ide device access 1 task file 3f7 atapi peripheral 4fh ide device access 1 dma interrupt reason dma controller 50h shows reason (source) for dma interrupt 2 section 9.4.6 on page 53 dma interrupt enable dma controller 54h enables dma interrupt sources 2 section 9.4.7 on page 55 dma endpoint dma controller 58h selects endpoint fifo, data ?ow direction 1 section 9.4.8 on page 56 dma strobe timing dma controller 60h strobe duration in mdma mode 1 section 9.4.9 on page 56 dma burst counter dma controller 64h dma burst length 2 section 9.4.10 on page 57 general registers interrupt device 18h shows interrupt sources 4 section 9.5.1 on page 57 chip id device 70h product id code and hardware version 3 section 9.5.2 on page 59 frame number device 74h last successfully received start of frame: lower byte (byte 0) is accessed ?rst 2 section 9.5.3 on page 60 scratch device 78h allows save or restore of ?rmware status during suspend 2 section 9.5.4 on page 60 unlock device device 7ch re-enables register access after suspend 2 section 9.5.5 on page 61 test mode phy 84h direct setting of the dp and dm states, internal transceiver test (phy) 1 section 9.5.6 on page 62 table 18: register overview continued name destination address description size (bytes) reference
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 29 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? buffer length ? buffer status ? control function ? data port ? endpoint maxpacketsize ? endpoint type. remark: all reserved bits are not implemented. the bus and bus reset values are not de?ned. therefore, writing to these reserved bits will have no effect. 9.2 initialization registers 9.2.1 address register (address: 00h) this register sets the usb assigned address and enables the usb device. ta b l e 1 9 shows the address register bit allocation. bits devaddr will be cleared whenever a bus reset, a power-on reset or a soft reset occurs. bit deven will be cleared whenever a power-on reset or a soft reset occurs, and will be set after a bus reset. in response to the standard usb request set_address, the ?rmware must write the (enabled) device address to the address register, followed by sending an empty packet to the host. the new device address is activated when the device receives acknowledgment from the host. 9.2.2 mode register (address: 0ch) this register consists of 2 bytes (bit allocation: see ta b l e 2 1 ). the mode register controls resume, suspend and wake-up behavior, interrupt activity, soft reset, clock signals and softconnect operation. table 19: address register: bit allocation bit 7 6 5 4 3 2 1 0 symbol deven devaddr[6:0] reset 00000000 bus reset 10000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 20: address register: bit description bit symbol description 7 deven logic 1 enables the device. 6 to 0 devaddr[6:0] this ?eld speci?es the usb device address.
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 30 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 21: mode register: bit allocation bit 15 14 13 12 11 10 9 8 symbol test2 test1 test0 reserved dma clkon vbusstat reset ------0- bus reset ------0- access rrrrrrr/wr bit 7 6 5 4 3 2 1 0 symbol clkaon sndrsu gosusp sfreset glintena wkupcs pwron softct reset 00000000 bus reset 0000 unchanged 0 0 unchanged access r/w r/w r/w r/w r/w r/w r/w r/w table 22: mode register: bit description bit symbol description 15 test2 this bit re?ects the mode1 pin setting. only for test purposes. 14 test1 this bit re?ects the mode0 pin setting. only for test purposes. 13 test0 this bit re?ects the bus_conf pin setting. only for test purposes. 12 to 10 - reserved 9 dmaclkon 0 power save mode; the dma circuit will stop completely to save power. 1 supply clock to the dma circuit. 8 vbusstat this bit re?ects the v bus pin status. 7 clkaon clock always on: logic 1 indicates that the internal clocks are always running when in the suspend state. logic 0 switches off the internal oscillator and pll when the device goes into suspend mode. the device will consume less power if this bit is set to logic 0. the clock is stopped after a delay of approximately 2 ms, following which bit gosusp is set. 6 sndrsu send resume: writing logic 1, followed by logic 0 will generate an upstream resume signal of 10 ms duration, after a 5 ms delay. 5 gosusp go suspend: writing logic 1, followed by logic 0 will activate suspend mode. 4 sfreset soft reset: writing logic 1, followed by logic 0 will enable a software-initiated reset to the ISP1583. a soft reset is similar to a hardware-initiated reset (via the reset_n pin).
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 31 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. when softconnect and v bus are not present (except in otg), the usb bus activities are not quali?ed. therefore, the chip will follow the suspend command to enter suspend mode (the clock is controlled by bit clkaon). when v bus is off, the 1.5 k w pull-up resister is disconnected from pin dp in approximately 4 ns via bit softct in the mode register and a suspend interrupt is set with some latency (debounce and disqualify usb traf?c). when bit softct is set to logic 0, no interrupt is generated. the ?rmware can issue a suspend command, followed by the resetting of bit softct to suspend the chip. if otg is logic 1, the pull-up resistor on pin dp depends on d+ line (v bus sensing status). bit dp operates as normal, so the ?rmware must mask suspend and wake-up interrupt events. when srp is completed, the device should clear otg. if otg is logic 0, the status of the pull-up resistor on dp is referred to in ta b l e 2 3 . 3 glintena global interrupt enable: logic 1 enables all interrupts. individual interrupts can be masked by clearing the corresponding bits in the interrupt enable register. when this bit is not set, an unmasked interrupt will not generate an interrupt trigger on the interrupt pin. if global interrupt, however, is enabled while there is any pending unmasked interrupt, an interrupt signal will be immediately generated on the interrupt pin. (if the interrupt is set to pulse mode, the interrupt events that were generated before the global interrupt is enabled may be dropped.) 2 wkupcs wake-up on chip selection: logic 1 enables wake-up from suspend mode through a valid register read on the ISP1583. (a read will invoke the chip clock to restart. if you write to the register before the clock gets stable, it may cause malfunctioning.) 1 pwron the suspend pin output control. 0 the suspend pin is high when the ISP1583 is in the suspend state. otherwise, the suspend pin is low. 1 when the device is woken up from the suspend state, there will be a 1 ms active high pulse on the suspend pin. the suspend pin will remain low in all other states. 0 softct softconnect: logic 1 enables the connection of the 1.5 k w pull-up resistor on pin rpu to the dp line. bus reset value: unchanged. table 23: status of the chip v bus softconnect = on softconnect = off on pull-up resistor on dp pull-up resistor on dp is removed; suspend interrupt is immediately set, regardless of the d+ and d - signals off pull-up resistor on dp is removed; suspend interrupt is immediately set, regardless of the d+ and d - signals pull-up resistor on dp is removed; suspend interrupt is immediately set, regardless of the d+ and d - signals table 22: mode register: bit description continued bit symbol description
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 32 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.2.3 interrupt con?guration register (address: 10h) this 1-byte register determines the behavior and polarity of the int output. the bit allocation is shown in ta b l e 2 4 . when the usb sie receives or generates an ack, nak or stall, it will generate interrupts depending on three debug mode ?elds. cdbgmod[1:0] interrupts for the control endpoint 0 ddbgmodin[1:0] interrupts for the data in endpoints 1 to 7 ddbgmodout[1:0] interrupts for the data out endpoints 1 to 7. the debug mode settings for cdbgmod, ddbgmodin and ddbgmodout allow you to individually con?gure when the ISP1583 sends an interrupt to the external microprocessor. ta b l e 2 6 lists the available combinations. bit intpol controls the signal polarity of the int output: active high or low, rising or falling edge. for level-triggering, bit intlvl must be made logic 0. by setting intlvl to logic 1, an interrupt will generate a pulse of 60 ns (edge-triggering). [1] first nak: the ?rst nak on an in or out token after a previous ack response. 9.2.4 otg register (address: 12h) the bit allocation of the otg register is given in ta b l e 2 7 . table 24: interrupt con?guration register: bit allocation bit 7 6 5 4 3 2 1 0 symbol cdbgmod[1:0] ddbgmodin[1:0] ddbgmodout[1:0] intlvl intpol reset 11111100 bus reset 111111 unchanged unchanged access r/w r/w r/w r/w r/w r/w r/w r/w table 25: interrupt con?guration register: bit description bit symbol description 7 to 6 cdbgmod[1:0] control 0 debug mode: for values, see ta bl e 2 6 5 to 4 ddbgmodin[1:0] data debug mode in: for values, see ta b l e 2 6 3 to 2 ddbgmodout[1:0] data debug mode out: for values, see ta b l e 2 6 1 intlvl interrupt level : selects signaling mode on output int (0 = level; 1 = pulsed). in pulsed mode, an interrupt produces a 60 ns pulse. bus reset value: unchanged. 0 intpol interrupt polarity: selects signal polarity on output int (0 = active low, 1 = active high). bus reset value: unchanged. table 26: debug mode settings value cdbgmod ddbgmodin ddbgmodout 00h interrupt on all ack and nak interrupt on all ack and nak interrupt on all ack, nyet and nak 01h interrupt on all ack. interrupt on ack interrupt on ack and nyet 1xh interrupt on all ack and ?rst nak [1] interrupt on all ack and ?rst nak [1] interrupt on all ack, nyet and ?rst nak [1]
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 33 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 27: otg register: bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved dp bsessvalid initcond discv vp otg reset --0 - -000 bus reset --0 - -000 access - - r/w r/w r/w r/w r/w r/w table 28: otg register: bit description [1] bit symbol description 7 to 6 - reserved 5 dp when set, data-line pulsing is started. the default value of this bit is logic 0. this bit must be cleared when data-line pulsing is completed. 4 bsessvalid the device can initiate another v bus discharge sequence after data-line pulsing and v bus pulsing, and before it clears this bit and detects a session valid. this bit is latched to logic 1 once v bus exceeds the b-device session valid threshold. once set, it remains at logic 1. to clear this bit, write logic 1. (the ISP1583 continuously updates this bit to logic 1 when the b-session is valid. if the b-session is valid after it is cleared, it is set back to logic 1 by the ISP1583). 0 it implies that srp has failed. to proceed to a normal operation, the device can restart srp, clear bit otg or proceed to an error handling process. 1 it implies that the b-session is valid. the device clears bit otg, goes into normal operation mode, and sets bit softct (dp pull-up) in the mode register. the otg host has a maximum of 5 s before it responds to a session request. during this period, the ISP1583 may request to suspend. therefore, the device ?rmware must wait for sometime if it wishes to know the srp result (successif there is minimum response from the host within 5 s; failureif there is no response from the host within 5 s). 3 initcond write logic 1 to clear this bit. the device clears this bit, and waits for more than 2 ms to check the bit status. if it reads logic 0, it means that v bus remains lower than 0.8 v, and dp or dm at se0 during the elapsed time is cleared. the device can then start a b-device srp. if it reads logic 1, it means that the initial condition of an srp is violated. so, the device should abort srp. the bit is set to logic 1 by the ISP1583 when initial conditions are not met, and only writing logic 1 clears the bit. (if initial conditions are not met after this bit has been cleared, it will be set again). remark: this implementation does not cover the case if an initial srp condition is violated when this bit is read and data-line pulsing is started.
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 34 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] no interrupt is designed for otg. the v bus interrupt, however, may assert as a side effect during the v bus pulsing (see note 2). when otg is in progress, the v bus interrupt may be set because v bus is charged over v bus sensing threshold or the otg host has turned on the v bus supply to the device. even if the v bus interrupt is found during srp, the device should complete data-line pulsing and v bus pulsing before starting the b_session_valid detection. otg implementation applies to the device with self-power capability. if the device works in sharing mode, it should provide a switch circuit to supply power to the ISP1583 core during srp. session request protocol (srp): the ISP1583 can initiate an srp. the b-device initiates srp by data-line pulsing followed by v bus pulsing. the a-device can detect either data-line pulsing or v bus pulsing. the ISP1583 can initiate the b-device srp by performing the following steps: 1. detect initial conditions: read bit initcond of the otg register. 2. start data-line pulsing: set bit dp of the otg register to logic 1. 3. wait for 5 ms to 10 ms. 4. stop data-line pulsing: set bit dp of the otg register to logic 0. 5. start v bus pulsing: set bit vp of the otg register to logic 1. 6. wait for 10 ms to 20 ms. 7. stop v bus pulsing: set bit vp of the otg register to logic 0. 8. discharge v bus for about 30 ms: optional by using bit discv of the otg register. 9. detect bit bsessvalid of the otg register for a successful srp with bit otg disabled. the b-device must complete both data-line pulsing and v bus pulsing within 100 ms. remark: when disabling, otg data-line pulsing bit dp and v bus pulsing bit vp must be cleared by writing logic 1. 9.2.5 interrupt enable register (address: 14h) this register enables or disables individual interrupt sources. the interrupt for each endpoint can be individually controlled via the associated bits iepnrx or iepntx, here n represents the endpoint number. all interrupts can be globally disabled through bit glintena in the mode register (see ta b l e 2 1 ). 2 discv set to logic 1 to discharge v bus . the device discharges v bus before starting a new srp. the discharge can take as long as 30 ms for v bus to be charged less than 0.8 v. this bit must be cleared (write logic 0) before starting a session end detection. 1 vp set to logic 1 to start v bus pulsing. this bit must be set for more than 16 ms and must be cleared before 26 ms. 0otg 1 enables the otg function. the v bus sensing functionality will be bypassed. 0 normal operation. all otg control bits will be masked. status bits are unde?ned. table 28: otg register: bit description [1] continued bit symbol description
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 35 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. an interrupt is generated when the usb sie receives or generates an ack or nak on the usb bus. the interrupt generation depends on debug mode settings of bit ?elds cdbgmod[1:0], ddbgmodin[1:0] and ddbgmodout[1:0]. all data in transactions use the transmit buffers (tx), which are handled by bits ddbgmodin. all data out transactions go via the receive buffers (rx), which are handled by bits ddbgmodout. transactions on control endpoint 0 (in, out and setup) are handled by bits cdbgmod. interrupts caused by events on the usb bus (sof, pseudo sof, suspend, resume, bus reset, setup and high-speed status) can also be individually controlled. a bus reset disables all enabled interrupts except bit iebrst (bus reset), which remains unchanged. the interrupt enable register consists of 4 bytes. the bit allocation is given in ta b l e 2 9 . table 29: interrupt enable register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved iep7tx iep7rx reset ------00 bus reset ------00 access - - - - - - r/w r/w bit 23 22 21 20 19 18 17 16 symbol iep6tx iep6rx iep5tx iep5rx iep4tx iep4rx iep3tx iep3rx reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol iep2tx iep2rx iep1tx iep1rx iep0tx iep0rx reserved iep0setup reset 000000- 0 bus reset 000000- 0 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol ievbus iedma iehs_sta ieresm iesusp iepsof iesof iebrst reset 00000000 bus reset 0000000 unchanged access r/w r/w r/w r/w r/w r/w r/w r/w table 30: interrupt enable register: bit description bit symbol description 31 to 26 - reserved 25 iep7tx logic 1 enables interrupt from the indicated endpoint. 24 iep7rx logic 1 enables interrupt from the indicated endpoint. 23 iep6tx logic 1 enables interrupt from the indicated endpoint. 22 iep6rx logic 1 enables interrupt from the indicated endpoint. 21 iep5tx logic 1 enables interrupt from the indicated endpoint.
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 36 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.3 data ?ow registers 9.3.1 endpoint index register (address: 2ch) the endpoint index register selects a target endpoint for register access by the microcontroller. the register consists of 1 byte, and the bit allocation is shown in ta b l e 3 1 . the following registers are indexed: ? buffer length ? buffer status ? control function ? data port ? endpoint maxpacketsize ? endpoint type. for example, to access the out data buffer of endpoint 1 using the data port register, the endpoint index register has to be written ?rst with 02h. remark: the endpoint index register and the dma endpoint index register must not point to the same endpoint. 20 iep5rx logic 1 enables interrupt from the indicated endpoint. 19 iep4tx logic 1 enables interrupt from the indicated endpoint. 18 iep4rx logic 1 enables interrupt from the indicated endpoint. 17 iep3tx logic 1 enables interrupt from the indicated endpoint. 16 iep3rx logic 1 enables interrupt from the indicated endpoint. 15 iep2tx logic 1 enables interrupt from the indicated endpoint. 14 iep2rx logic 1 enables interrupt from the indicated endpoint. 13 iep1tx logic 1 enables interrupt from the indicated endpoint. 12 iep1rx logic 1 enables interrupt from the indicated endpoint. 11 iep0tx logic 1 enables interrupt from the control in endpoint 0. 10 iep0rx logic 1 enables interrupt from the control out endpoint 0. 9 - reserved 8 iep0setup logic 1 enables interrupt for the setup data received on endpoint 0. 7 ievbus logic 1 enables interrupt for v bus sensing. 6 iedma logic 1 enables interrupt on dma status change detection. 5 iehs_sta logic 1 enables interrupt on detection of a high-speed status change. 4 ieresm logic 1 enables interrupt on detection of a resume state. 3 iesusp logic 1 enables interrupt on detection of a suspend state. 2 iepsof logic 1 enables interrupt on detection of a pseudo sof. 1 iesof logic 1 enables interrupt on detection of an sof. 0 iebrst logic 1 enables interrupt on detection of a bus reset. table 30: interrupt enable register: bit description continued bit symbol description
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 37 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.3.2 control function register (address: 28h) the control function register performs the buffer management on endpoints. it consists of 1 byte, and the bit con?guration is given in ta b l e 3 4 . the register bits can stall, clear or validate any enabled data endpoint. before accessing this register, the endpoint index register must be written ?rst to specify the target endpoint. table 31: endpoint index register: bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved ep0setup endpidx[3:0] dir reset - - 000000 bus reset - - 000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 32: endpoint index register: bit description bit symbol description 7 to 6 - reserved 5 ep0setup selects the setup buffer for endpoint 0. 0 ep0 data buffer 1 setup buffer. must be logic 0 for access to other endpoints than endpoint 0. 4 to 1 endpidx[3:0] endpoint index: selects the target endpoint for register access of buffer length, control function, data port, endpoint type and maxpacketsize. 0 dir direction bit: sets the target endpoint as in or out. 0 target endpoint refers to out (rx) fifo 1 target endpoint refers to in (tx) fifo. table 33: addressing of endpoint 0 buffers buffer name ep0setup endpidx dir setup 1 00h 0 data out 0 00h 0 data in 0 00h 1 table 34: control function register: bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved clbuf vendp dsen status stall reset - - - 00000 bus reset - - - 00000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 38 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.3.3 data port register (address: 20h) this 2-byte register provides direct access for a microcontroller to the fifo of the indexed endpoint. the bit allocation is shown in ta b l e 3 6 . peripheral-to-host (in endpoint): after each write action, an internal counter is auto incremented (by two for a 16-bit access, by one for an 8-bit access) to the next location in the tx fifo. when all bytes have been written (fifo byte count = endpoint maxpacketsize), the buffer is automatically validated. the data packet will then be sent on the next in token. when it is necessary to validate the endpoint whose byte count is less than maxpacketsize, it can be done using the control function register (bit vendp). host-to-peripheral (out endpoint) : after each read action, an internal counter is auto decremented (by two for a 16-bit access, by one for an 8-bit access) to the next location in the rx fifo. when all bytes have been read, the buffer contents are automatically cleared. a new data packet can then be received on the next out token. the buffer contents can also be cleared through the control function register (bit clbuf), when it is necessary to forcefully clear the contents. table 35: control function register: bit description bit symbol description 7 to 5 - reserved. 4 clbuf clear buffer: logic 1 clears the rx buffer of the indexed endpoint; the tx buffer is not affected. the rx buffer is automatically cleared once the endpoint is completely read. this bit is set only when it is necessary to forcefully clear the buffer. 3 vendp validate endpoint: logic 1 validates the data in the tx fifo of an in endpoint for sending on the next in token. in general, the endpoint is automatically validated when its fifo byte count has reached the endpoint maxpacketsize. this bit is set only when it is necessary to validate the endpoint with the fifo byte count which is below the endpoint maxpacketsize. 2 dsen data stage enable : this bit controls the response of the ISP1583 to a control transfer. when this bit is set, the ISP1583 goes to the data stage; otherwise, the ISP1583 will nak the data stage transfer until the ?rmware explicitly responds to the setup command. 1 status status acknowledge: only applicable for control in/out. this bit controls the generation of ack or nak during the status stage of a setup transfer. it is automatically cleared when the status stage is completed, or when a setup token is received. no interrupt signal will be generated. 0 sends nak 1 sends an empty packet following the in token (host-to-peripheral) or ack following the out token (peripheral-to-host). 0 stall stall endpoint : logic 1 stalls the indexed endpoint. this bit is not applicable for isochronous transfers. remark: stalling a data endpoint will confuse the data toggle bit about the stalled endpoint because the internal logic picks up from where it is stalled. therefore, the data toggle bit must be reset by disabling and re-enabling the corresponding endpoint (by setting bit enable to logic 0 or logic 1 in the endpoint type register) to reset the pid.
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 39 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. remark: the buffer can be automatically validated or cleared by using the buffer length register (see ta b l e 3 8 ). 9.3.4 buffer length register (address: 1ch) this register determines the current packet size (datacount) of the indexed endpoint fifo. the bit allocation is given in ta b l e 3 8 . the buffer length register is automatically loaded with the fifo size, when the endpoint maxpacketsize register is written (see ta b l e 4 2 ). a smaller value can be written when required. after a bus reset, the buffer length register is made zero. in endpoint: when data transfer is performed in multiples of maxpacketsize, the buffer length register is not signi?cant. this register is useful only when transferring data that is not a multiple of maxpacketsize. the following two examples demonstrate the signi?cance of the buffer length register. example 1: consider that the transfer size is 512 bytes and the maxpacketsize is programmed as 64 bytes, the buffer length register need not be ?lled. this is because the transfer size is a multiple of maxpacketsize, and the maxpacketsize packets will be automatically validated because the last packet is also of maxpacketsize. example 2: consider that the transfer size is 510 bytes and the maxpacketsize is programmed as 64 bytes, the buffer length register should be ?lled with 62 bytes just before the mcu writes the last packet of 62 bytes. this ensures that the last packet, which is a short packet of 62 bytes, is automatically validated. use bit vendp in the control register if you are not using the buffer length register. this is applicable only to pio mode access. out endpoint: the datacount value is automatically initialized to the number of data bytes sent by the host on each ack. table 36: data port register: bit allocation bit 15 14 13 12 11 10 9 8 symbol dataport[15:8] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dataport[7:0] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 37: data port register: bit description bit symbol description 15 to 8 dataport[15:8] data (upper byte) 7 to 0 dataport[7:0] data (lower byte)
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 40 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. remark: when using a 16-bit microprocessor bus, the last byte of an odd-sized packet is output as the lower byte (lsbyte). remark: buffer length is valid only after an interrupt is generated for the bulk endpoint. 9.3.5 buffer status register (address: 1eh) this register is accessed using index. the endpoint index must ?rst be set before accessing this register for the corresponding endpoint. it re?ects the status of the double buffered endpoint fifo. this register is valid only when the endpoint is con?gured to be a double buffer. remark: this register is not applicable to the control endpoint. ta b l e 4 0 shows the bit allocation of the buffer status register. table 38: buffer length register: bit allocation bit 15 14 13 12 11 10 9 8 symbol datacount[15:8] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol datacount[7:0] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 39: buffer length register: bit description bit symbol description 15 to 0 datacount[15:0] determines the current packet size of the indexed endpoint fifo. table 40: buffer status register: bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved buf1 buf0 reset ------00 bus reset ------00 access ------rr table 41: buffer status register: bit description bit symbol description 7 to 2 - reserved 1 to 0 buf[1:0] 00 the buffers are not ?lled. 01 one of the buffers is ?lled. 10 one of the buffers is ?lled. 11 both buffers are ?lled.
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 41 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.3.6 endpoint maxpacketsize register (address: 04h) this register determines the maximum packet size for all endpoints except control 0. the register contains 2 bytes, and the bit allocation is given in ta b l e 4 2 . each time the register is written, the buffer length registers of all endpoints are reinitialized to the ffosz ?eld value. bits ntrans control the number of transactions allowed in a single microframe (for high-speed isochronous and interrupt endpoints only). table 42: endpoint maxpacketsize register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved ntrans[1:0] ffosz[10:8] reset - - - 00000 bus reset - - - 00000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol ffosz[7:0] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 43: endpoint maxpacketsize register: bit description bit symbol description 15 to 13 - reserved 12 to 11 ntrans[1:0] number of transactions (hs mode only). 00 1 packet per microframe 01 2 packets per microframe 10 3 packets per microframe 11 reserved. these bits are applicable only for isochronous or interrupt transactions. 10 to 0 ffosz[10:0] fifo size : sets the fifo size, in bytes, for the indexed endpoint. applies to both high-speed and full-speed operations (see ta b l e 4 4 ). table 44: programmable fifo size ntrans[1:0] ffosz[10:0] non-isochronous isochronous 0h 08h 8 bytes - 0h 10h 16 bytes - 0h 20h 32 bytes - 0h 40h 64 bytes - 0h 80h 128 bytes - 0h 100h 256 bytes - 0h 200h 512 bytes - 2h 400h - 3072 bytes
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 42 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. each programmable fifo can be independently con?gured via its endpoint maxpacketsize register (r/w: 04h), but the total physical size of all enabled endpoints (in plus out) must not exceed 8192 bytes. 9.3.7 endpoint type register (address: 08h) this register sets the endpoint type of the indexed endpoint: isochronous, bulk or interrupt. it also serves to enable the endpoint and con?gure it for double buffering. automatic generation of an empty packet for a zero-length tx buffer can be disabled using bit noempkt. the register contains 2 bytes, and the bit allocation is shown in ta b l e 4 5 . table 45: endpoint type register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- bus reset -------- access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved noempkt enable dblbuf endptyp[1:0] reset - - - 00000 bus reset - - - 00000 access r/w r/w r/w r/w r/w r/w r/w r/w table 46: endpoint type register: bit description bit symbol description 15 to 5 - reserved 4 noempkt no empty packet: logic 0 causes the ISP1583 to return a null length packet for the in token after the dma in transfer is complete. for ata mode or the dma in transfer, which does not require a null length packet after dma completion, set to logic 1 to disable the generation of the null length packet. 3 enable endpoint enable : logic 1 enables the fifo of the indexed endpoint. the memory size is allocated as speci?ed in the endpoint maxpacketsize register. logic 0 disables the fifo. remark: stalling a data endpoint will confuse the data toggle bit on the stalled endpoint because the internal logic picks up from where it has stalled. therefore, the data toggle bit must be reset by disabling and re-enabling the corresponding endpoint (by setting bit enable to logic 0 or logic 1 in the endpoint type register) to reset the pid. 2 dblbuf double buffering: logic 1 enables double buffering for the indexed endpoint. logic 0 disables double buffering. 1 to 0 endptyp[1:0] endpoint type: these bits select the endpoint type. 00 not used 01 isochronous 10 bulk 11 interrupt.
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 43 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.4 dma registers two types of generic dma transfer and three types of ide-speci?ed transfer can be done by writing the proper opcode in the dma command register. the control bits are given in ta b l e 4 7 (generic dma transfers) and ta b l e 4 8 (ide-speci?ed transfers). gdma read/write (opcode = 00h/01h) generic dma slave mode. depending on the mode[1:0] bit set in the dma con?guration register, either the dack signal or the dior/diow signals strobe the data. these signals are driven by the external dma controller. gdma slave mode can operate in either counter mode or eot-only mode. in counter mode, bit dis_xfer_cnt in the dma con?guration register must be set to logic 0. the dma transfer counter register must be programmed before any dma command is issued. the dma transfer counter is set by writing from the lsbyte to the msbyte (address: 34h to 37h). the dma transfer count is internally updated only after the msbyte has been written. once the dma transfer is started, the transfer counter starts decrementing and on reaching 0, bit dma_xfer_ok is set and an interrupt is generated by the ISP1583. if the dma master wishes to terminate the dma transfer, it can issue an eot signal to the ISP1583. this eot signal overrides the transfer counter and can terminate the dma transfer at any time. in eot-only mode, dis_xfer_cnt has to be set to logic 1. although the dma transfer counter can still be programmed, it will not have any effect on the dma transfer. the dma transfer will start once the dma command is issued. any of the following three ways will terminate this dma transfer: ? detecting an external eot ? detecting an internal eot (short packet on an out token) ? resetting the dma. there are three interrupts programmable to differentiate the method of dma termination: bits int_eot, ext_eot and dma_xfer_ok in the dma interrupt reason register (see ta b l e 7 2 ). mdma (master) read/write (opcode = 06h/07h) generic dma master mode. depending on the mode[1:0] bit set in the dma con?guration register, either the dack signal or the dior/diow signals strobe the data. these signals are driven by the ISP1583. in master mode, burstcounter[12:0] in the dma burst counter register, dis_xfer_cnt in the dma con?guration register and the external eot signal are not applicable. the dma transfer counter is always enabled and bit dma_xfer_ok is set to 1 once the counter reaches 0. mdma read/write (opcode = 06h/07h) multiword dma mode for ide transfers. the speci?cation of this mode can be obtained from the ata speci?cation rev. 4 . dior and diow are used as data strobes, while dreq and dack serve as handshake signals.
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 44 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. remark: the dma bus defaults to 3-state, until a dma command is executed. all the other control signals are not 3-state. 9.4.1 dma command register (address: 30h) the dma command register is a 1-byte register (for bit allocation, see ta b l e 4 9 ) that initiates all dma transfer activity on the dma controller. the register is write-only: reading it will return ffh. remark: the dma bus will be in 3-state until a dma command is executed. table 47: control bits for generic dma transfers control bits description reference gdma read/write (opcode = 00h/01h) mdma (master) read/write (opcode = 06h/07h) dma con?guration register ata_mode set to logic 0 (non-ata transfer) set to logic 1 (ata transfer) ta b l e 5 4 dma_mode[1:0] - determines mdma timings for dior and diow strobes dis_xfer_cnt disables use of dma transfer counter disables use of dma transfer counter mode[1:0] determines active read/write data strobe signals determines active data strobe(s) width selects dma bus width: 8 or 16 bits selects dma bus width: 8 or 16 bits dma hardware register endian[1:0] determines whether data is to be byte swapped or normal; applicable only in 16-bit mode determines whether data is to be byte swapped or normal; applicable only in 16-bit mode ta b l e 5 6 eot_pol selects polarity of eot signal input eot is not used master set to logic 0 (slave) set to logic 1 (master) ack_pol, dreq_pol, write_pol, read_pol selects polarity of dma handshake signals selects polarity of dma handshake signals table 48: control bits for ide-speci?ed dma transfers control bits description reference mdma read/write (opcode = 06h/07h) dma con?guration register ata_mode set to logic 1 (ata transfer) ta b l e 5 4 dma_mode[1:0] selects mdma mode; timings are ata(pi) compatible pio_mode[2:0] selects pio mode; timings are ata(pi) compatible dma hardware register master set to logic 0 ta b l e 5 6
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 45 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 49: dma command register: bit allocation bit 7 6 5 4 3 2 1 0 symbol dma_cmd[7:0] reset 11111111 bus reset 11111111 access wwwwwwww table 50: dma command register: bit description bit symbol description 7 to 0 dma_cmd[7:0] dma command code, see ta b l e 5 1 . pio read or write that started using dma command register only performs a 16-bit transfer. table 51: dma commands code name description 00h gdma read generic dma in token transfer (slave mode only): data is transferred from the external dma bus to the internal buffer. strobe: diow by external dma controller. 01h gdma write generic dma out token transfer (slave mode only): data is transferred from the internal buffer to the external dma bus. strobe: dior by external dma controller. 02h to 05h - reserved 06h mdma read multiword dma read: data is transferred from the external dma bus to the internal buffer. 07h mdma write multiword dma write: data is transferred from the internal buffer to the external dma bus. 0ah read 1f0 read at address 1f0h: initiates a pio read cycle from task file 1f0. before issuing this command, the task ?le byte count should be programmed at address 1f4h (lsb) and 1f5h (msb). 0bh poll bsy poll bsy status bit for atapi device: starts repeated pio read commands to poll the bsy status bit of the atapi device. when bsy = 0, polling is terminated and an interrupt is generated. the interrupt can be masked but the interrupt bit will still be set. therefore, you can manually poll this interrupt bit. 0ch read task files read task files: reads all task ?les. when task file index is set to logic 0, this command reads all registers, except 1f0h and 1f7h. if task file index is not logic 0, the task register of the address set in the task file register will be read. when the reading is completed, an interrupt is generated. the interrupt could be masked off, however, the interrupt bit will still be set. therefore, you can manually poll this interrupt bit. 0dh - reserved 0eh validate buffer validate buffer (for debugging only): request from the microcontroller to validate the endpoint buffer following an ata-to-usb data transfer.
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 46 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.4.2 dma transfer counter register (address: 34h) this 4-byte register sets up the total byte count for a dma transfer (dmacr). it indicates the remaining number of bytes left for transfer. the bit allocation is given in ta b l e 5 2 . for in endpoint as there is a fifo in the ISP1583 dma controller, some data may remain in the fifo during the dma transfer. the maximum fifo size is 8 bytes, and the maximum delay time for the data to be shifted to endpoint buffer is 60 ns. 0fh clear buffer clear buffer: request from the microcontroller to clear the endpoint buffer after a usb-to-ata data transfer. 10h restart restart: request from the microcontroller to move the buffer pointers to the beginning of the endpoint fifo. 11h reset dma reset dma: initializes the dma core to its power-on reset state. remark: when the dma core is reset during the reset dma command, the dreq, dack, diow and dior handshake pins will be temporarily asserted. this can confuse the external dma controller. to prevent this, start the external dma controller only after the dma reset. 12h mdma stop mdma stop: this command immediately stops the mdma data transfer. this is applicable for commands 06h and 07h only. 13h gdma stop gdma stop : this command stops the gdma data transfer. any data in the out endpoint that is not transferred by the dma will remain in the buffer. the fifo data for the in endpoint will be written to the endpoint buffer. an interrupt bit will be set to indicate the completion of the dma stop command. 14h to 20h - reserved 21h read task file register 1f1h read task file register 1f1h : when reading has been completed, an interrupt is generated. 22h read task file register 1f2h read task file register 1f2h : when reading has been completed, an interrupt is generated. 23h read task file register 1f3h read task file register 1f3h : when reading has been completed, an interrupt is generated. 24h read task file register 1f4h read task file register 1f4h : when reading has been completed, an interrupt is generated. 25h read task file register 1f5h read task file register 1f5h : when reading has been completed, an interrupt is generated. 26h read task file register 1f6h read task file register 1f6h: . when reading has been completed, an interrupt is generated. 27h read task file register 3f6h read task file register 3f6h : when reading has been completed, an interrupt is generated. 28h read task file register 3f7h read task file register 3f7h : when reading has been completed, an interrupt is generated. 29h to ffh - reserved table 51: dma commands continued code name description
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 47 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. for out endpoint data will not be cleared for the endpoint buffer until all the data has been read from the dma fifo. if the dma counter is disabled in the dma transfer, it will still decrement and rollover when it reaches zero. 9.4.3 dma con?guration register (address: 38h) this register de?nes the dma con?guration for gdma mode. the dma con?guration register consists of 2 bytes. the bit allocation is given in ta b l e 5 4 . table 52: dma transfer counter register: bit allocation bit 31 30 29 28 27 26 25 24 symbol dmacr4 = dmacr[31:24] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol dmacr3 = dmacr[23:16] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol dmacr2 = dmacr[15:8] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dmacr1 = dmacr[7:0] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 53: dma transfer counter register: bit description bit symbol description 31 to 24 dmacr4, dmacr[31:24] dma transfer counter byte 4 (msb) 23 to 16 dmacr3, dmacr[23:16] dma transfer counter byte 3 15 to 8 dmacr2, dmacr[15:8] dma transfer counter byte 2 7 to 0 dmacr1, dmacr[7:0] dma transfer counter byte 1 (lsb) table 54: dma con?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved ata_ mode dma_mode[1:0] pio_mode[2:0] reset 0 0000000 bus reset 0 0000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 48 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. bit 7 6 5 4 3 2 1 0 symbol dis_ xfer_cnt reserved mode[1:0] reserved width reset 0 0000001 bus reset 0 0000001 access r/w r/w r/w r/w r/w r/w r/w r/w table 55: dma con?guration register: bit description [1] bit symbol description 15 to 14 - reserved 13 ata_mode mode selection of the dma core. 0 con?gures the dma core for ata or mdma mode. used when issuing dma commands 02h to 07h, 0ah and 0ch; also used when directly accessing task file registers. 1 con?gures the dma core for non-ata mode. used when issuing dma commands 00h and 01h. 13 ata_mode logic 1 con?gures the dma core for ata or mdma mode. used when issuing dma commands 02h to 07h, 0ah and 0ch; also used when directly accessing task file registers. logic 0 con?gures the dma core for non-ata mode. used when issuing dma commands 00h and 01h. 12 to 11 dma_mode[1:0] these bits affect the timing for mdma mode. 00 mdma mode 0: ata(pi) compatible timings 01 mdma mode 1: ata(pi) compatible timings 10 mdma mode 2: ata(pi) compatible timings 11 mdma mode 3: enables the dma strobe timing register (see ta b l e 7 7 and ta bl e 7 8 ) for non-standard strobe durations; only used in mdma mode. 10 to 8 pio_mode[2:0] [2] these bits affect the pio timing. 000 to 100 pio mode 0 to 4: ata(pi) compatible timings 101 to 111 reserved. 7 dis_xfer_cnt logic 1 disables the dma transfer counter (see ta b l e 5 2 ). the transfer counter can be disabled only in gdma slave mode; in master mode the counter is always enabled. 6 to 4 - reserved
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 49 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] the dreq pin will be driven only after performing a write access to the dma con?guration register (that is, after con?guring the dma con?guration register). [2] pio read or write that started using dma command register only performs 16-bit transfer. 9.4.4 dma hardware register (address: 3ch) the dma hardware register consists of 1 byte. the bit allocation is shown in ta b l e 5 6 . this register determines the polarity of the bus control signals (eot, dack, dreq, dior and diow) and dma mode (master or slave). it also controls whether the upper and lower parts of the data bus are swapped (bits endian[1:0]), for modes gdma (slave) and mdma (master) only. 3 to 2 mode[1:0] these bits only affect the gdma (slave) and mdma (master) handshake signals. 00 dior (master) or diow (slave): strobes data from the dma bus into the ISP1583; diow (master) or dior (slave): puts data from the ISP1583 on the dma bus. 01 dior (master) or dack (slave): strobes the data from the dma bus into the ISP1583; dack (master) or dior (slave): puts the data from the ISP1583 on the dma bus. 10 dack (master and slave): strobes the data from the dma bus into the ISP1583 and also puts the data from the ISP1583 on the dma bus (this mode is applicable only to the 16-bit dma; this mode cannot be used for the 8-bit dma.). 11 reserved. 1 - reserved 0 width this bit selects the dma bus width for gdma (slave) and mdma (master). 0 8-bit data bus. 1 16-bit data bus. table 55: dma con?guration register: bit description [1] continued bit symbol description table 56: dma hardware register: bit allocation bit 7 6 5 4 3 2 1 0 symbol endian[1:0] eot_pol master ack_pol dreq_ pol write_ pol read_ pol reset 00000100 bus reset 00000100 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 50 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.4.5 task file registers (addresses: 40h to 4fh) these registers allow direct access to the internal registers of an atapi peripheral using pio mode. the supported task file registers and their functions are shown in ta b l e 5 8 . the correct peripheral register is automatically addressed via pins cs1_n, cs0_n, da2, da1 and da0 (see ta b l e 5 9 ). table 57: dma hardware register: bit description bit symbol description 7 to 6 endian[1:0] these bits determine whether the data bus is swapped between the internal ram and the dma bus. this only applies for modes gdma (slave) and mdma (master). 00 normal data representation; 16-bit bus: msb on data[15:8] and lsb on data[7:0]. 01 swapped data representation; 16-bit bus: msb on data[7:0] and lsb on data[15:8]. 10 reserved. 11 reserved. remark: while operating with the 8-bit data bus, bits endian[1:0] should be always set to logic 00. 5 eot_pol selects the polarity of the end-of-transfer input; used in gdma slave mode only. 0 eot is active low 1 eot is active high. 4 master selects dma master/slave mode. 0 gdma slave mode 1 mdma master mode. 3 ack_pol selects the dma acknowledgment polarity. 0 dack is active low 1 dack is active high. 2 dreq_pol selects the dma request polarity. 0 dreq is active low 1 dreq is active high. 1 write_pol selects the diow strobe polarity. 0 diow is active low 1 diow is active high. 0 read_pol selects the dior strobe polarity. 0 dior is active low 1 dior is active high.
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 51 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. in 8-bit bus mode, the 16-bit task file register 1f0 requires two consecutive write/read accesses before the proper pio write/read is generated on the ide interface. the ?rst byte is always the lower byte (lsbyte). other task file registers can be directly accessed. writing to task file registers can be done in any order except for the task file register 1f7, which must be written last. table 58: task file register functions task ?le ata function atapi function 1f0 data (16-bits) data (16-bits) 1f1 error/feature error/feature 1f2 sector count interrupt reason 1f3 sector number/lba[7:0] reserved 1f4 cylinder low/lba[15:8] cylinder low 1f5 cylinder high/lba[23:16] cylinder high 1f6 drive/head/lba[27:24] drive select 1f7 command status/command 3f6 alternate status/command alternate status/command 3f7 drive address reserved table 59: atapi peripheral register addressing task ?le cs1_n cs0_n da2 da1 da0 1f0 hllll 1f1 hlllh 1f2 h l l h l 1f3 h l l h h 1f4 hl hl l 1f5 hl hl h 1f6 hl hhl 1f7 hl hhh 3f6 l hhhl 3f7 l hhhh table 60: task file 1f0 register (address: 40h): bit allocation cs1_n = h, cs0_n = l, da2 = l, da1 = l, da0 = l. bit 7 6 5 4 3 2 1 0 symbol data (ata or atapi) reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 52 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 61: task file 1f1 register (address: 48h): bit allocation cs1_n = h, cs0_n = l, da2 = l, da1 = l, da0 = h. bit 7 6 5 4 3 2 1 0 symbol error/feature (ata or atapi) reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 62: task file 1f2 register (address: 49h): bit allocation cs1_n = h, cs0_n = l, da2 = l, da1 = h, da0 = l. bit 7 6 5 4 3 2 1 0 symbol sector count (ata) or interrupt reason (atapi) reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 63: task file 1f3 register (address: 4ah): bit allocation cs1_n = h, cs0_n = l, da2 = l, da1 = h, da0 = h. bit 7 6 5 4 3 2 1 0 symbol sector number/lba[7:0] (ata), reserved (atapi) reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 64: task file 1f4 register (address: 4bh): bit allocation cs1_n = h, cs0_n = l, da2 = h, da1 = l, da0 = l. bit 7 6 5 4 3 2 1 0 symbol cylinder low/lba[15:8] (ata) or cylinder low (atapi) reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 65: task file 1f5 register (address: 4ch): bit allocation cs1_n = h, cs0_n = l, da2 = h, da1 = l, da0 = h. bit 7 6 5 4 3 2 1 0 symbol cylinder high/lba[23:16] (ata) or cylinder high (atapi) reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 53 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] task file register 1f7 is a write-only register; a read will return ffh. 9.4.6 dma interrupt reason register (address: 50h) this 2-byte register shows the source(s) of dma interrupt. each bit is refreshed after a dma command has been executed. an interrupt source is cleared by writing logic 1 to the corresponding bit. when reading, and the value of the bits in this register with the value of the corresponding bits in the dma interrupt enable register. the bit allocation is given in ta b l e 7 0 . table 66: task file 1f6 register (address: 4dh): bit allocation cs1_n = h, cs0_n = l, da2 = h, da1 = h, da0 = l. bit 7 6 5 4 3 2 1 0 symbol drive/head/lba[27:24] (ata) or drive (atapi) reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 67: task file 1f7 register (address: 44h): bit allocation cs1_n = h, cs0_n = l, da2 = h, da1 = h, da0 = h. bit 7 6 5 4 3 2 1 0 symbol command (ata) or status [1] /command (atapi) reset 00000000 bus reset 00000000 access wwwwwwww table 68: task file 3f6 register (address: 4eh): bit allocation cs1_n = l, cs0_n = h, da2 = h, da1 = h, da0 = l. bit 7 6 5 4 3 2 1 0 symbol alternate status/command (ata or atapi) reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 69: task file 3f7 register (address: 4fh): bit allocation cs1_n = l, cs0_n = h, da2 = h, da1 = h, da0 = h. bit 7 6 5 4 3 2 1 0 symbol drive address (ata) or reserved (atapi) reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 54 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 70: dma interrupt reason register: bit allocation bit 15 14 13 12 11 10 9 8 symbol test3 reserved gdma_ stop ext_eot int_eot intrq_ pending dma_ xfer_ok reset - - - 00000 bus reset - - - 00000 access r r r r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved read_1f0 bsy_ done tf_rd_ done cmd_ intrq_ok reserved reset 0000000 - bus reset 0000000 - access r/w r/w r/w r/w r/w r/w r/w r/w table 71: dma interrupt reason register: bit description bit symbol description 15 test3 this bit is set when a dma transfer for a packet (out transfer) terminates before the whole packet has been transferred. this bit is a status bit, and the corresponding mask bit of this register is always 0. writing any value other than 0 has no effect. 14 to 13 - reserved 12 gdma_stop when the gdma_stop command is issued to the dma command registers, it means the dma transfer has successfully terminated. 11 ext_eot logic 1 indicates that an external eot is detected. this is applicable only in gdma slave mode. 10 int_eot logic 1 indicates that an internal eot is detected; see ta b l e 7 2 . 9 intrq_ pending logic 1 indicates that a pending interrupt was detected on pin intrq. 8 dma_xfer_ok logic 1 indicates that the dma transfer has been completed (dma transfer counter has become zero). this bit is only used in gdma (slave) mode and mdma (master) mode. 7 to 5 - reserved 4 read_1f0 logic 1 indicates that the 1f0 fifo contains unread data and the microcontroller can start reading data. 3 bsy_done logic 1 indicates that the bsy status bit has become zero and polling has been stopped. 2 tf_rd_done logic 1 indicates that the read task files command has been completed. 1 cmd_intrq_ok logic 1 indicates that all bytes from the fifo have been transferred (dma transfer count zero) and an interrupt on pin intrq was detected. 0 - reserved
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 55 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. ta b l e 7 3 shows the status of the bits in the dma interrupt reason register when the corresponding bits in the interrupt register is set. [1] 1 indicates that the bit is set and 0 indicates that the bit is not set. a bit is set when the corresponding eot condition is met. for example; ext_eot is set if external eot conditions are met (pin eot active), regardless of other eot conditions. if multiple eot conditions are met, the corresponding interrupt bits are set. if both ext_eot and dma_xfer_ok conditions are met in dma for an in endpoint, the ext_eot interrupt is not set. [2] the value of int_eot may not be accurate if an external or internal transfer counter is programmed with a value that is lower than the transfer that the host requests. to terminate an out transfer with int_eot, the external or internal dma counter should be programmed as a multiple of the full-packet length of the dma endpoint. when a short packet is successfully transferred by dma, int_eot is set. 9.4.7 dma interrupt enable register (address: 54h) this 2-byte register controls the interrupt generation of the source bits in the dma interrupt reason register (see ta b l e 7 0 ). the bit allocation is given in ta b l e 7 4 . the bit description is given in ta b l e 7 1 . logic 1 enables interrupt generation. after a bus reset, interrupt generation is disabled, with the values turning to logic 0. table 72: internal eot-functional relation with dma_xfer_ok bit int_eot dma_ xfer_ok description 1 0 during the dma transfer, there is a premature termination with short packet. 1 1 dma transfer is completed with short packet and the dma transfer counter has reached 0. 0 1 dma transfer is completed without any short packet and the dma transfer counter has reached 0. table 73: status of the bits in the dma interrupt reason register [1] status ext_eot int_eot dma_xfer_ok counter enabled counter disabled in full 1 0 1 0 in short 1 0 1 0 out full 1 0 1 0 out short 1 1 [2] 10 table 74: dma interrupt enable register: bit allocation bit 15 14 13 12 11 10 9 8 symbol test4 reserved ie_gdma_ stop ie_ext_ eot ie_int_ eot ie_intrq_ ending ie_dma_ xfer_ok reset - - - 00000 bus reset - - - 00000 access r - - r/w r/w r/w r/w r/w
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 56 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.4.8 dma endpoint register (address: 58h) this 1-byte register selects a usb endpoint fifo as a source or destination for dma transfers. the bit allocation is given in ta b l e 7 5 . the dma endpoint register must not reference the endpoint that is indexed by the endpoint index register (2ch) at any time. doing so would result in data corruption. therefore, if the dma endpoint register is unused, point it to an unused endpoint. if the dma endpoint register, however, is pointed to an active endpoint, the ?rmware must not reference the same endpoint on the endpoint index register. 9.4.9 dma strobe timing register (address: 60h) this 1-byte register controls the strobe timing for mdma mode, when bits dma_mode in the dma con?guration register have been set to 03h. the bit allocation is given in ta b l e 7 7 . bit 7 6 5 4 3 2 1 0 symbol reserved ie_ read_1f0 ie_bsy_ done ie_tf_ rd_done ie_cmd_ intrq_ok reserved reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 75: dma endpoint register: bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved epidx[2:0] dmadir reset ---- 0000 bus reset ---- 0000 access ----r/wr/wr/wr/w table 76: dma endpoint register: bit description bit symbol description 7 to 4 - reserved 3 to 1 epidx[2:0] selects the indicated endpoint for dma access 0 dmadir 0 selects the rx/out fifo for dma read transfers 1 selects the tx/in fifo for dma write transfers. table 77: dma strobe timing register: bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved dma_strobe_cnt[4:0] reset - - - 11111 bus reset - - - 11111 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 57 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] the cycle duration indicates the internal clock cycle (33.3 ns/cycle). 9.4.10 dma burst counter register (address: 64h) 9.5 general registers 9.5.1 interrupt register (address: 18h) the interrupt register consists of 4 bytes. the bit allocation is given in ta b l e 8 1 . table 78: dma strobe timing register: bit description bit symbol description 7 to 5 - reserved. 4 to 0 dma_strobe_ cnt[4:0] these bits select the strobe duration for dma_mode = 03h (see ta b l e 5 4 ). the strobe duration is (n + 1) cycles [1] , with n representing the value of dma_strobe_cnt (see figure 16 ). fig 16. programmable strobe timing. x x (n + 1) cycles 004aaa125 table 79: dma burst counter register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved burstcounter[12:8] reset - - - 00000 bus reset - - - 00000 access - - - r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol burstcounter[7:0] reset 00000010 bus reset 00000010 access r/w r/w r/w r/w r/w r/w r/w r/w table 80: dma burst counter register: bit description bit symbol description 15 to 13 - reserved 12 to 0 burstcounter[12:0] this register de?nes the burst length. the counter must be programmed to be a multiple of two in 16-bit mode. the value of the burst counter should be programmed such that the buffer counter is a factor of the burst counter. for in endpoint when the burst counter equals 2, in gdma mode, dreq will drop at every dma read or write cycle.
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 58 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. when a bit is set in the interrupt register, it indicates that the hardware condition for an interrupt has occurred. when the interrupt register content is nonzero, the int output will be asserted corresponding to the interrupt enable register. on detecting the interrupt, the external microprocessor must read the interrupt register and mask it with the corresponding bits in the interrupt enable register to determine the source of the interrupt. each endpoint buffer has a dedicated interrupt bit (epntx, epnrx). in addition, various bus states can generate an interrupt: resume, suspend, pseudo sof, sof and bus reset. the dma controller only has one interrupt bit: the source for a dma interrupt is shown in the dma interrupt reason register (see ta b l e 7 0 and ta b l e 7 1 ). each interrupt bit can be individually cleared by writing logic 1. the dma interrupt bit can be cleared by writing logic 1 to the related interrupt source bit in the dma interrupt reason register and writing logic 1 to the dma bit of the interrupt register. table 81: interrupt register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved ep7tx ep7rx reset -----000 bus reset -----000 access -----r/wr/wr/w bit 23 22 21 20 19 18 17 16 symbol ep6tx ep6rx ep5tx ep5rx ep4tx ep4rx ep3tx ep3rx reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol ep2tx ep2rx ep1tx ep1rx ep0tx ep0rx reserved ep0setup reset 000000- 0 bus reset 000000- 0 access r/w r/w r/w r/w r/w r/w - r/w bit 7 6 5 4 3 2 1 0 symbol vbus dma hs_stat resume susp psof sof breset reset 00000000 bus reset 0000000 unchanged access r/w r/w r/w r/w r/w r/w r/w r/w table 82: interrupt register: bit description bit symbol description 31 to 26 - reserved 25 ep7tx logic 1 indicates the endpoint 7 tx buffer as interrupt source. 24 ep7rx logic 1 indicates the endpoint 7 rx buffer as interrupt source. 23 ep6tx logic 1 indicates the endpoint 6 tx buffer as interrupt source. 22 ep6rx logic 1 indicates the endpoint 6 rx buffer as interrupt source. 21 ep5tx logic 1 indicates the endpoint 5 tx buffer as interrupt source.
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 59 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.5.2 chip id register (address: 70h) this read-only register contains the chip identi?cation and the hardware version numbers. the ?rmware should check this information to determine the functions and features supported. the register contains 3 bytes, and the bit allocation is shown in ta b l e 8 3 . 20 ep5rx logic 1 indicates the endpoint 5 rx buffer as interrupt source. 19 ep4tx logic 1 indicates the endpoint 4 tx buffer as interrupt source. 18 ep4rx logic 1 indicates the endpoint 4 rx buffer as interrupt source. 17 ep3tx logic 1 indicates the endpoint 3 tx buffer as interrupt source. 16 ep3rx logic 1 indicates the endpoint 3 rx buffer as interrupt source. 15 ep2tx logic 1 indicates the endpoint 2 tx buffer as interrupt source. 14 ep2rx logic 1 indicates the endpoint 2 rx buffer as interrupt source. 13 ep1tx logic 1 indicates the endpoint 1 tx buffer as interrupt source. 12 ep1rx logic 1 indicates the endpoint 1 rx buffer as interrupt source. 11 ep0tx logic 1 indicates the endpoint 0 data tx buffer as interrupt source. 10 ep0rx logic 1 indicates the endpoint 0 data rx buffer as interrupt source. 9 - reserved 8 ep0setup logic 1 indicates that a setup token was received on endpoint 0. 7 vbus logic 1 indicates v bus is turned on. 6 dma dma status: logic 1 indicates a change in the dma status register. 5 hs_stat high speed status: logic 1 indicates a change from full-speed to high-speed mode (hs connection). this bit is not set, when the system goes into full-speed suspend. 4 resume resume status: logic 1 indicates that a status change from suspend to resume (active) was detected. 3 susp suspend status: logic 1 indicates that a status change from active to suspend was detected on the bus. 2 psof pseudo sof interrupt: logic 1 indicates that a pseudo sof or m sof was received. pseudo sof is an internally generated clock signal (full-speed: 1 ms period, high-speed: 125 m s period) synchronized to the usb bus sof or m sof. 1 sof sof interrupt: logic 1 indicates that a sof or m sof was received. 0 breset bus reset : logic 1 indicates that a usb bus reset was detected. when bit otg in the otg register is set, breset will not be set, instead, this interrupt bit will report se0 on dp and dm for 2 ms. table 82: interrupt register: bit description continued bit symbol description table 83: chip id register: bit allocation bit 23 22 21 20 19 18 17 16 symbol chipid[15:8] reset 00010101 bus reset 00010101 access rrrrrrrr
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 60 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.5.3 frame number register (address: 74h) this read-only register contains the frame number of the last successfully received start-of-frame (sof). the register contains 2 bytes, and the bit allocation is given in ta b l e 8 5 . in case of 8-bit access, the register content is returned lower byte ?rst. 9.5.4 scratch register (address: 78h) this 16-bit register can be used by the ?rmware to save and restore information. for example, the device status before it enters the suspend state. the bit allocation is given in ta b l e 8 7 . bit 15 14 13 12 11 10 9 8 symbol chipid[7:0] reset 10000010 bus reset 10000010 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol version[7:0] reset 00110000 bus reset 00110000 access rrrrrrrr table 84: chip id register: bit description bit symbol description 23 to 16 chipid[15:8] chip id: lower byte (15h) 15 to 8 chipid[7:0] chip id: upper byte (82h) 7 to 0 version[7:0] version number (30h) table 85: frame number register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved microsof[2:0] sofr[10:8] power reset - - 000000 bus reset - - 000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol sofr[7:0] power reset 00000000 bus reset 00000000 access rrrrrrrr table 86: frame number register: bit description bit symbol description 15 to 14 - reserved 13 to 11 microsof[2:0] microframe number 10 to 0 sofr[10:0] frame number
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 61 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.5.5 unlock device register (address: 7ch) to protect the registers from getting corrupted when the ISP1583 goes into suspend, the write operation is disabled if bit pwron in the mode register is set to logic 0. in this case, when the chip resumes, the unlock device command must be ?rst issued to this register before attempting to write to the rest of the registers. this is done by writing unlock code (aa37h) to this register. the bit allocation of the unlock device register is given in ta b l e 8 9 . when bit pwron in the mode register is logic 1, the chip is powered. in such a case, you do not need to issue the unlock command because the microprocessor is powered and therefore, the rd_n, wr_n and cs_n signals maintain their states. table 87: scratch register: bit allocation bit 15 14 13 12 11 10 9 8 symbol sfirh[7:0] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol sfirl[7:0] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 88: scratch register: bit description bit symbol description 15 to 8 sfirh[7:0] scratch ?rmware information register (higher byte) 7 to 0 sfirl[7:0] scratch ?rmware information register (lower byte) table 89: unlock device register: bit allocation bit 15 14 13 12 11 10 9 8 symbol ulcode[15:8] = aah reset not applicable bus reset not applicable access wwwwwwww bit 7 6 5 4 3 2 1 0 symbol ulcode[7:0] = 37h reset not applicable bus reset not applicable access wwwwwwww table 90: unlock device register: bit description bit symbol description 15 to 0 ulcode[15:0] writing data aa37h unlocks the internal registers and fifos for writing, following a resume.
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 62 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. when bit pwron is logic 0, the rd_n, wr_n and cs_n signals are ?oating because the microprocessor is not powered. to protect the ISP1583 registers from being corrupted during suspend, register write is locked when the chip goes into suspend. therefore, you need to issue the unlock command to unlock the ISP1583 registers. 9.5.6 test mode register (address: 84h) this 1-byte register allows the ?rmware to set the dp and dm pins to predetermined states for testing purposes. the bit allocation is given in ta b l e 9 1 . remark: only one bit can be set at a time. either bit forcehs or bit forcefs should be set to logic 1 at a time. of the four bits prbs, kstate, jstate and se0_nak only one bit should be set at a time. this must be implemented for the hi-speed usb logo compliance testing. table 91: test mode register: bit allocation bit 7 6 5 4 3 2 1 0 symbol forcehs reserved forcefs prbs kstate jstate se0_nak reset 0 - - 00000 bus reset 0 - - 00000 access r/w r/w r/w r/w r/w r/w r/w r/w table 92: test mode register: bit description bit symbol description 7 forcehs logic 1 forces the hardware to high-speed mode only and disables the chirp detection logic. 6 to 5 - reserved. 4 forcefs logic 1 forces the physical layer to full-speed mode only and disables the chirp detection logic. 3 prbs logic 1 sets the dp and dm pins to toggle in a predetermined random pattern. 2 kstate logic 1 sets the dp and dm pins to the k state. 1 jstate logic 1 sets the dp and dm pins to the j state. 0 se0_nak logic 1 sets the dp and dm pins to a high-speed quiescent state. the device only responds to a valid high-speed in token with a nak.
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 63 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10. limiting values [1] the maximum value for 5 v tolerant pins is 6 v. 11. recommended operating conditions 12. static characteristics table 93: absolute maximum ratings in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc(3v3) supply voltage - 0.5 +4.6 v v cc(i/o) i/o pad supply voltage - 0.5 +4.6 v v i input voltage [1] - 0.5 v cc(3v3) + 0.5 v i lu latch-up current v i < 0 or v i >v cc(3v3) - 100 ma v esd electrostatic discharge voltage i li <1 m a pins dp, dm, v bus , agnd and dgnd - 4000 +4000 v other pins - 2000 +2000 v t stg storage temperature - 40 +125 c table 94: recommended operating conditions symbol parameter conditions min max unit v cc(3v3) supply voltage 3.0 3.6 v v cc(i/o) i/o pad supply voltage 1.65 3.6 v v i input voltage range v cc(3v3) = 3.3 v 0 5.5 v v i(ai/o) input voltage on analog i/o pins dp and dm 0 3.6 v v o(pu) open-drain output pull-up voltage 0 v cc(3v3) v t amb ambient temperature - 40 +85 c table 95: static characteristics: supply pins v cc(3v3) = 3.3 v 0.3 v; v gnd =0v; t amb = - 40 cto+85 c; typical values at t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supply voltage v cc(3v3) supply voltage 3.0 3.3 3.6 v i cc(3v3) operating supply current v cc(3v3) = 3.3 v high-speed - 47 60 ma full-speed - 19 25 ma i cc(3v3)(susp) suspend supply current v cc(3v3) = 3.3 v - 160 - m a i/o pad supply voltage v cc(i/o) i/o pad supply voltage 1.65 3.3 3.6 v i cc(i/o) operating supply current v cc(i/o) = 3.3 v high-speed - 150 200 m a full-speed - 80 120 m a
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 64 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] this value is applicable to transistor input only. the value will be different if internal pull-up or pull-down resistors ar e used. i cc(i/o)(susp) suspend supply current v cc(i/o) = 3.3 v - 5 10 m a regulated supply voltage v cc(1v8) regulated supply output voltage with voltage converter 1.65 1.8 1.95 v table 95: static characteristics: supply pins continued v cc(3v3) = 3.3 v 0.3 v; v gnd =0v; t amb = - 40 cto+85 c; typical values at t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit table 96: static characteristics: digital pins v cc(i/o) = 1.65 v to 3.6 v; v gnd =0v; t amb = - 40 cto+85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit input levels v il low-level input voltage - - 0.3v cc(i/o) v v ih high-level input voltage 0.7v cc(i/o) -- v output levels v ol low-level output voltage i ol = rated drive - - 0.15v cc(i/o) v v oh high-level output voltage i oh = rated drive 0.8v cc(i/o) -- v leakage current i li input leakage current [1] - 5- +5 m a table 97: static characteristics: otg detection v cc(i/o) = 1.65 v to 3.6 v; v gnd =0v; t amb = - 40 cto+85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit charging and discharging resistor r pd discharging resistor 684.8 843.5 1032 w r pu charging resistor 551.9 666.7 780.6 w comparator levels v bvalid v bus valid detection v cc(i/o) = 3.3 v 0.3 v 2.0 - 4.0 v v sesend v bus b-session end detection v cc(i/o) = 3.3 v 0.3 v 0.2 - 0.8 v table 98: static characteristics: analog i/o pins dp and dm [1] v cc(3v3) = 3.3 v 0.3 v; v gnd =0v; t amb = - 40 cto+85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit input levels v di differential input sensitivity | v i(dp) - v i(dm) | 0.2 - - v v cm differential common mode voltage includes v di range 0.8 - 2.5 v v se single-ended receiver threshold 0.8 2.0 v v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v schmitt-trigger inputs v th(lh) positive-going threshold voltage 1.4 - 1.9 v v th(hl) negative-going threshold voltage 0.9 - 1.5 v v hys hysteresis voltage 0.4 - 0.7 v
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 65 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] pin dp is the usb positive data pin and pin dm is the usb negative data pin. 13. dynamic characteristics output levels v ol low-level output voltage r l = 1.5 k w to 3.6 v - - 0.4 v v oh high-level output voltage r l =15k w to gnd 2.8 - 3.6 v leakage current i lz off-state leakage current 0 < v i < 3.3 v - 10 - +10 m a capacitance c in transceiver capacitance pin to gnd - - 10 pf resistance z drv driver output impedance steady-state drive 40.5 - 49.5 w z inp input impedance 10 - - m w table 98: static characteristics: analog i/o pins dp and dm [1] continued v cc(3v3) = 3.3 v 0.3 v; v gnd =0v; t amb = - 40 cto+85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit table 99: dynamic characteristics v cc(3v3) = 3.3 v 0.3 v; v gnd =0v; t amb = - 40 cto+85 c; unless otherwise speci?ed. symbol parameter conditions min. typ max unit reset t w(reset_n) pulse width on pin reset_n crystal oscillator running 500 - - m s crystal oscillator f xtal crystal frequency - 12 - mhz r s series resistance - - 100 w c l load capacitance - 18 - pf external clock input t j external clock jitter - - 500 ps d clock duty cycle 45 50 55 % t r , t f rise time and fall time - - 3 ns v in input voltage 1.65 1.8 1.95 v table 100: dynamic characteristics: analog i/o pins dp and dm v cc(3v3) = 3.3 v 0.3 v; v gnd =0v; t amb = - 40 cto+85 c; c l = 50 pf; r pu = 1.5 k w on dp to v term .; test circuit of figure 36 ; unless otherwise speci?ed. symbol parameter conditions min. typ max unit driver characteristics full-speed mode t fr rise time c l =50pf; 10%to90% of | v oh - v ol | 4 - 20 ns t ff fall time c l =50pf; 90 % to 10 % of | v oh - v ol | 4 - 20 ns frfm differential rise time and fall time matching (t fr /t ff ) [1] 90 - 111.11 % v crs output signal crossover voltage [1][2] 1.3 - 2.0 v
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 66 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] excluding the ?rst transition from the idle state. [2] characterized only, not tested. limits guaranteed by design. high-speed mode t hsr high-speed differential rise time with captive cable 500 - - ps t hsf high-speed differential fall time with captive cable 500 - - ps data source timing full-speed mode t feopt source eop width see figure 17 [2] 160 - 175 ns t fdeop source differential data-to-eop transition skew see figure 17 [2] - 2 - +5 ns receiver timing full-speed mode t jr1 receiver data jitter tolerance to next transition see figure 18 [2] - 18.5 - +18.5 ns t jr2 receiver data jitter tolerance for paired transitions see figure 18 [2] - 9 - +9 ns t feopr receiver se0 width accepted as eop; see figure 17 [2] 82 - - ns t fst width of se0 during differential transition rejected as eop; see figure 19 [2] - - 14 ns table 100: dynamic characteristics: analog i/o pins dp and dm continued v cc(3v3) = 3.3 v 0.3 v; v gnd =0v; t amb = - 40 cto+85 c; c l = 50 pf; r pu = 1.5 k w on dp to v term .; test circuit of figure 36 ; unless otherwise speci?ed. symbol parameter conditions min. typ max unit t period is the bit duration corresponding with the usb data rate. full-speed timing symbols have a subscript pre?x f, low-speed timing symbols have a pre?x l. fig 17. source differential data-to-eop transition skew and eop width. mgr776 t period differential data lines crossover point differential data to se0/eop skew n t period + t deop source eop width: t eopt receiver eop width: t eopr crossover point extended + 3.3 v 0 v
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 67 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.1 register access timing 13.1.1 generic processor mode bus_conf = h: generic processor mode: ? mode0 = h: 8051 style; see figure 20 ? mode0 = l: motorola style; see figure 21 . t period is the bit duration corresponding with the usb data rate. fig 18. receiver differential data jitter. mgr871 t period t jr differential data lines + 3.3 v 0 v t jr1 t jr2 consecutive transitions n t period + t jr1 paired transitions n t period + t jr2 fig 19. receiver se0 width tolerance. mgr872 differential data lines + 3.3 v 0 v t fst v ih(min) table 101: ISP1583 register access timing parameters: separate address and data buses v cc(i/o) = 3.3 v; v cc(3v3) = 3.3 v; v gnd =0v; t amb = - 40 cto+85 c. symbol parameter min max unit reading t rlrh rd_n low pulse width >t rldv -ns t avrl address set-up time before rd_n low 0 - ns t rhax address hold time after rd_n high 0 - ns t rldv rd_n low to data valid delay - 26 ns t rhdz rd_n high to data outputs 3-state delay 0 15 ns t rhsh rd_n high to cs_n high delay 0 - ns t slrl cs_n low to rd_n low delay 2 - ns
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 68 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. writing t wlwh wr_n low pulse width 15 - ns t avwl address set-up time before wr_n low 0 - ns t whax address hold time after wr_n high 0 - ns t dvwh data set-up time before wr_n high 11 - ns t whdz data hold time after wr_n high 5 - ns t whsh wr_n high to cs_n high delay 0 - ns t slwl cs_n low to wr_n low delay 2 - ns general t cy(rw) read/write cycle time 50 - ns t i1vi2l rw_n set-up time before ds_n low 0 - ns t i2hi1x rw_n hold time after ds_n high 0 - ns t rdy1 ready high to rd_n/wr_n high of the last access - 91 ns table 101: ISP1583 register access timing parameters: separate address and data buses continued v cc(i/o) = 3.3 v; v cc(3v3) = 3.3 v; v gnd =0v; t amb = - 40 cto+85 c. symbol parameter min max unit fig 20. ISP1583 register access timing: separate address and data buses (8051 style). (write) data [ 15:0 ] (read) data [ 15:0 ] 004aaa301 ad [ 7:0 ] t whsh t avwl t dvwh t rhdz t avrl t cy(rw) t whax t rhax t rldv t whdz wr_n cs_n rd_n t rhsh t rlrh t wlwh t slwl t slrl
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 69 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 21. ISP1583 register access timing: separate address and data buses (motorola style). (write) data [ 15:0 ] write (read) data [ 15:0 ] read 004aaa379 ad [ 7:0 ] t whsh t avwl t dvwh t i1vi2l t i2hi1x t cy(rw) t whax t whdz rw_n ds_n cs_n t wlwh fig 22. ISP1583 ready signal timing. 004aaa380 t rdy1 wr_n ready (1) programmable polarity: shown as active low. remark: eot should be valid for 36 ns (minimum) when rd_n/wr_n is active. fig 23. eot timing in generic processor mode. eot (1) rd_n, wr_n 004aaa378 36 ns (min) dreq t h1
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 70 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.1.2 split bus mode ale function: ? bus_conf = l: split bus mode ? mode1 = l: ale function C mode0 = h: 8051 style; see figure 24 C mode0 = l: motorola style; see figure 25 . table 102: ISP1583 register access timing parameters: multiplexed address/data bus v cc(i/o) = 3.3 v; v cc(3v3) = 3.3 v; v gnd =0v; t amb = - 40 cto+85 c. symbol parameter min max unit reading t rlrh rd_n low pulse width >t rldv -ns t rldv rd_n low to data valid delay - 25 ns t rhdz rd_n high to data outputs 3-state delay 0 15 ns t rhsh rd_n high to cs_n high delay 0 - ns t llrl ale low set-up time before rd_n low 0 - ns writing t wlwh wr_n/ds_n low pulse width 15 - ns t dvwh data set-up time before wr_n high 5 - ns t llwl ale low to wr_n/ds_n low delay 0 - ns t whdz data hold time after wr_n/ds_n high 5 - ns t whsh wr_n/ds_n high to cs_n high delay 0 - ns general t cy(rw) read/write cycle time 80 - ns t avll address set-up time before ale low 0 - ns t i1vll rw_n set-up time before ale low 5 - ns t lli2l ale low to ds_n low delay 5 - ns t i2hi1x rw_n hold time after ds_n high 5 - ns
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 71 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 24. ISP1583 register access timing: multiplexed address/data bus (8051 style). address address data data (write) ad [ 7:0 ] ale (read) ad [ 7:0 ] t whsh t rhsh t rhdz t rldv t llwl t dvwh t llrl t whdz t avll 004aaa382 t cy(rw) wr_n cs_n rd_n t rlrh t wlwh fig 25. ISP1583 register access timing: multiplexed address/data bus (motorola style). address address data data (write) ad [ 7:0 ] ale (read) ad [ 7:0 ] t whsh t lli2l t dvwh t whdz t i2hi1x t i1vll 004aaa381 t cy(rw) rw_n ds_n cs_n t wlwh
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 72 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. a0 function: ? bus_conf = l: split bus mode ? mode1 = h: a0 function C mode0 = h: 8051 style; see figure 26 C mode0 = l: motorola style; see figure 27 . table 103: ISP1583 register access timing parameters: multiplexed address/data bus v cc(i/o) = 3.3 v; v cc(3v3) = 3.3 v; v gnd =0v; t amb = - 40 cto+85 c. symbol parameter min max unit reading t rldv rd_n low to data valid delay - 26 ns t rhdz rd_n high to data outputs 3-state delay 0 15 ns t rhsh rd_n high to cs_n high delay 0 - ns t rlrh rd_n low pulse width >t rldv -ns t whrh wr_n/ds_n high to rd_n high delay 40 - ns writing t a0wl a0 set-up time before wr_n/ds_n low 0 - ns t avwh address set-up time before wr_n/ds_n high 5 - ns t dvwh data set-up time before wr_n/ds_n high 5 - ns t whdz data hold time after wr_n/ds_n high 5 - ns t whsh wr_n/ds_n high to cs_n high delay 0 - ns t wlwh wr_n/ds_n low pulse width 15 - ns t whwh wr_n/ds_n high (address) to wr_n/ds_n high (data) delay 40 - ns general t cy(rw) read/write cycle time 50 - ns t i2hi1x rw_n hold time after ds_n high 5 - ns
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 73 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 26. ISP1583 register access timing: multiplexed address/data bus (a0 function and 8051 style). address address data data (write) ad [ 7:0 ] (read) ad [ 7:0 ] t whsh t rhsh t rhdz t rldv t dvwh t whdz t a0wl 004aaa383 t cy(rw) rd_n wr_n cs_n rd_n a0 t whrh t wlwh t whwh t avwh t rlrh wr_n
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 74 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 27. ISP1583 register access timing: multiplexed address/data bus (a0 function and motorola style). address address data data (write) ad [ 7:0 ] (read) ad [ 7:0 ] t whsh t rhsh t rhdz t rldv t dvwh t whdz t i2hi1x t a0wl 004aaa384 t cy(rw) rw_n ds_n cs_n rw_n a0 t whrh t wlwh t whwh t avwh t rlrh ds_n (1) programmable polarity: shown as active low. remark: eot should be valid for 36 ns (minimum) when dior/diow is active. fig 28. eot timing in split bus mode. eot (1) dior/diow (1) 36 ns (min) dreq t h1 004aaa012
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 75 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.2 dma timing 13.2.1 pio mode [1] t cy1 is the total cycle time, consisting of command active time t w1 and command recovery (inactive) time t w2 , that is, t cy1 =t w1 +t w2 . the minimum timing requirements for t cy1 , t w1 and t w2 must all be met. as t cy1(min) is greater than the sum of t w1(min) and t w2(min) , a host implementation must lengthen t w1 and/or t w2 to ensure that t cy1 is equal to or greater than the value reported in the identify device data. a device implementation shall support any legal host implementation. [2] t d2 speci?es the time after dior is negated, when the data bus is no longer driven by the device (3-state). [3] if iordy is low at t su4 , the host waits until iordy is made high before the pio cycle is completed. in that case, t su5 must be met for reading (t su3 does not apply). when iordy is high at t su4 , t su3 must be met for reading (t su5 does not apply). table 104: pio mode timing parameters v cc(i/o) = 3.3 v; v cc(3v3) = 3.3 v; v gnd =0v; t amb = - 40 cto+85 c. symbol parameter mode 0 mode 1 mode 2 mode 3 mode 4 unit t cy1(min) read/write cycle time [1] 600 383 240 180 120 ns t su1(min) address to dior/diow on set-up time 70 50 30 30 25 ns t w1(min) dior/diow pulse width [1] 165 125 100 80 70 ns t w2(min) dior/diow recovery time [1] ---7025ns t su2(min) data set-up time before diow off 60 45 30 30 20 ns t h2(min) data hold time after diow off 30 20 15 10 10 ns t su3(min) data set-up time before dior on 50 35 20 20 20 ns t h3(min) data hold time after dior off 55555ns t d2(max) data to 3-state delay after dior off [2] 30 30 30 30 30 ns t h1(min) address hold time after dior/diow off 20 15 10 10 10 ns t su4(min) iordy after dior/diow on set-up time [3] 35 35 35 35 35 ns t su5(min) read data to iordy high set-up time [3] 00000ns t w3(max) iordy low pulse width 1250 1250 1250 1250 1250 ns
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 76 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. (1) the device address consists of signals cs1_n, cs0_n, da2, da1 and da0. (2) the data bus width depends on the pio access command used. task file register access uses 8 bits (data[7:0]), except for the task file register 1f0 which uses 16 bits (data[15:0]). dma commands 04h and 05h also use a 16-bit data bus. (3) the device can negate iordy to extend the pio cycle with wait states. the host determines whether or not to extend the current cycle after t su4 following the assertion of dior or diow. the following three cases are distinguished: a) device keeps iordy released (high-impedance): no wait state is generated. b) device negates iordy during t su4 , but re-asserts iordy before t su4 expires: no wait state is generated. c) device negates iordy during t su4 and keeps iordy negated for at least 5 ns after t su4 expires: a wait state is generated. the cycle is completed as soon as iordy is re-asserted. for extended read cycles (dior asserted), the read data on lines datan must be valid at t d1 before iordy is asserted. (4) dior and diow have a programmable polarity: shown here as active low signals. fig 29. pio mode timing. high (write) data [ 7:0 ] (2) (read) data [ 7:0 ] (2) device (1) address valid dior, diow (4) iordy (3a) iordy (3b) iordy (3c) t w1 t w2 t h1 t su1 t su2 t su5 t su4 t su4 t w3 t h2 t su3 t d2 t h3 (min) t cy1 mgt499
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 77 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.2.2 gdma slave mode ? bits mode[1:0] = 00: data strobes dior (read) and diow (write); see figure 30 ? bits mode[1:0] = 01: data strobes dior (read) and dack (write); see figure 31 ? bits mode[1:0] = 10: data strobes dack (read and write); see figure 32 . table 105: gdma slave mode timing parameters v cc(i/o) = 3.3 v; v cc(3v3) = 3.3 v; v gnd =0v; t amb = - 40 cto+85 c. symbol parameter min max unit t cy1 read/write cycle time 75 - ns t su1 dreq set-up time before ?rst dack on 10 - ns t d1 dreq on delay after last strobe off 33.33 - ns t h1 dreq hold time after last strobe on 0 53 ns t w1 dior/diow pulse width 39 600 ns t w2 dior/diow recovery time 36 - ns t d2 read data valid delay after strobe on - 20 ns t h2 read data hold time after strobe off - 5 ns t h3 write data hold time after strobe off 1 - ns t su2 write data set-up time before strobe off 10 - ns t su3 dack setup time before dior/diow assertion 0 - ns t a1 dack deassertion after dior/diow deassertion 0 30 ns dreq is continuously asserted until the last transfer is done or the fifo is full. data strobes: dior (read), diow (write). (1) programmable polarity: shown as active low. (2) programmable polarity: shown as active high. fig 30. gdma slave mode timing: dior (master) and diow (slave). t h1 t w1 t su1 t d1 t su2 t d2 t h2 t cy1 (write) data [ 15:0 ] (read) data [ 15:0 ] dreq (2) dack (1) dior/diow (1) mgt500 t su3 t w2 t a1 t h3
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 78 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. dreq is asserted for every transfer. data strobes: dior (read), dack (write). (1) programmable polarity: shown as active low. (2) programmable polarity: shown as active high. fig 31. gdma slave mode timing: dior (master) or dack (slave). t d1 t w1 t su1 t h1 t su2 t d2 t h2 t cy1 (write) data [ 15:0 ] (read) data [ 15:0 ] dreq (2) dack (1) dior/diow (1) mgt502 t su3 t a1 t h3 dreq is continuously asserted until the last transfer is done or the fifo is full. data strobe: dack (read/write). (1) programmable polarity: shown as active low. (2) programmable polarity: shown as active high. fig 32. gdma slave mode timing: dack (master and slave). t h1 t w1 t su1 t d1 t su2 t d2 t h2 t cy1 (write) data [ 15:0 ] (read) data [ 15:0 ] dreq (2) high dack (1) dior/diow (1) mgt501 t w2 t h3
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 79 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.2.3 mdma mode [1] t cy1 is the total cycle time, consisting of command active time t w1 and command recovery (inactive) time t w2 , that is, t cy1 =t w1 +t w2 . the minimum timing requirements for t cy1 , t w1 and t w2 must all be met. as t cy1(min) is greater than the sum of t w1(min) and t w2(min) , a host implementation must lengthen t w1 and/or t w2 to ensure that t cy1 is equal to or greater than the value reported in the identify device data. a device implementation shall support any legal host implementation. table 106: mdma mode timing parameters v cc(i/o) = 3.3 v; v cc(3v3) = 3.3 v; v gnd =0v; t amb = - 40 cto+85 c. symbol parameter mode 0 mode 1 mode 2 unit t cy1(min) read/write cycle time [1] 480 150 120 ns t w1(min) dior/diow pulse width [1] 215 80 70 ns t d1(max) data valid delay after dior on 150 60 50 ns t h3(min) data hold time after dior off 555ns t su2(min) data set-up time before dior/diow off 100 30 20 ns t h2(min) data hold time after diow off 20 15 10 ns t su1(min) dack set-up time before dior/diow on 000ns t h1(min) dack hold time after dior/diow off 20 5 5 ns t w2(min) dior recovery time) [1] 50 50 25 ns diow recovery time [1] 215 50 25 ns t d2(max) dior on to dreq off delay 120 40 35 ns diow on to dreq off delay 40 40 35 ns t d3(max) dack off to data lines 3-state delay 20 25 25 ns (1) programmable polarity: shown as active low. (2) programmable polarity: shown as active high. fig 33. mdma master mode timing. (write) data [ 15:0 ] (read) data [ 15:0 ] dreq (2) dack (1) dior/diow (1) t w1 t w2 t su1 t su2 t d2 t su2 t h1 t h2 t h3 t cy1 mgt506 t d1 t d3
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 80 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 14. application information 15. test information the dynamic characteristics of the analog i/o ports dp and dm were determined using the circuit shown in figure 36 . fig 34. typical interface connections for generic processor mode. fig 35. typical interface connections for split bus mode (slave mode). 004aaa273 data read strobe 16 ISP1583 cpu data[15:0] rw_n/rd_n address 8 ad[7:0] write strobe ds_n/ wr_n chip select cs_n ale/a0 8 004aaa274 data [ 15:0 ] dreq ISP1583 dma 8051 microcontroller ad[7:0] int ale/a0 p0.7/ad7 to p0.0/ad0 ale dack diow dior write strobe read strobe interrupt address latch enable address/data rw_n/rd_n ds_n/ wr_n rd_n intn_n wr_n in full-speed mode, an internal 1.5 k w pull-up resistor is connected to pin dp. fig 36. load impedance for dp and dm pins (full-speed mode). test point c l 50 pf 15 k w d.u.t mgt495
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 81 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 16. package outline fig 37. hvqfn64 package outline. unit a max. a 1 d 1 a 4 bc e e h l e 1 y w v references outline version european projection issue date iec jedec jeita mm 1 0.05 0.00 0.80 0.65 0.30 0.18 0.5 7.5 e 2 7.5 0.2 4.85 4.55 d h 4.85 4.55 0.05 0.05 y 1 0.1 0.1 dimensions (mm are the original dimensions) 0.5 0.3 sot804-1 - - - mo-220 - - - 03-03-26 d 9.05 8.95 e 49 64 32 17 48 1 33 16 9.05 8.95 e 1 8.95 8.55 8.95 8.55 a detail x a 4 a 1 c d d 1 d h e 1 e 0 5 10 mm scale hvqfn64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 x 9 x 0.85 mm sot804-1 e e b y y 1 c c b a a c c b v m w m e 1 e 2 e h l terminal 1 index area terminal 1 index area 1/2 e 1/2 e x
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 82 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 17. soldering 17.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. in these situations re?ow soldering is recommended. 17.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 17.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 83 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 17.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 17.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . table 107: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5][6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 84 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vsop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages.
philips semiconductors ISP1583 hi-speed usb peripheral controller product data rev. 03 12 july 2004 85 of 87 9397 750 13461 ? koninklijke philips electronics n.v. 2004. all rights reserved. 18. revision history table 108: revision history rev date cpcn description 03 20040712 - product data (9397 750 13461) ? removed jaz ? ? figure 1 block diagram. : added 3.3 v to the rpu line ? table 2 pin description : updated description for pins 8, 10, 11, 12 and 63 ? section 8.8 softconnect : added the second paragraph ? table 4 ISP1583 pin status [1] : updated dreq ? table 18 register overview : removed loopback mode in description of fast mode register ? section 9.3.5 buffer status register (address: 1eh) : updated the ?rst paragraph and added a remark ? table 55 dma con?guration register: bit description [1] : added table note 1 ? table 99 dynamic characteristics : added v in ? table 104 pio mode timing parameters : updated table note 1 ? table 106 mdma mode timing parameters : updated table note 1. 02 20040503 - product data (9397 750 12978) 01 20040225 - preliminary data (9397 750 11497)
9397 750 13461 philips semiconductors ISP1583 hi-speed usb peripheral controller ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 03 12 july 2004 86 of 87 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 19. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 20. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 21. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 22. trademarks acpi is an open industry speci?cation for pc power management, co-developed by intel corp., microsoft corp. and toshiba onnow is a trademark of microsoft corp. softconnect is a trademark of koninklijke philips electronics n.v. zip is a registered trademark of iomega corp. level data sheet status [1] product status [2][3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2004. printed in the netherlands all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 12 july 2004 document order number: 9397 750 13461 contents philips semiconductors ISP1583 hi-speed usb peripheral controller 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 functional description . . . . . . . . . . . . . . . . . . . . . . . 12 8.1 dma interface, dma handler and dma registers. . . 13 8.2 hi-speed usb transceiver . . . . . . . . . . . . . . . . . . . . 13 8.3 mmu and integrated ram . . . . . . . . . . . . . . . . . . . . 13 8.4 microcontroller interface and microcontroller handler 14 8.5 otg srp module . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.6 philips high-speed transceiver . . . . . . . . . . . . . . . . . 14 8.6.1 philips parallel interface engine (pie) . . . . . . . . . . . 14 8.6.2 peripheral circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.6.3 hs detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.7 philips serial interface engine (sie) . . . . . . . . . . . . 15 8.8 softconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.9 system controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.10 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.11 output pins status . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.12 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.12.1 interrupt output pin . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.12.2 interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.13 v bus sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.14 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.15 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.15.1 power-sharing mode . . . . . . . . . . . . . . . . . . . . . . . . 22 8.15.2 self-powered mode . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.15.3 bus-powered mode . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 register description . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.1 register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.2 initialization registers . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2.1 address register (address: 00h). . . . . . . . . . . . . . . . 29 9.2.2 mode register (address: 0ch) . . . . . . . . . . . . . . . . . 29 9.2.3 interrupt con?guration register (address: 10h) . . . . 32 9.2.4 otg register (address: 12h) . . . . . . . . . . . . . . . . . . 32 9.2.5 interrupt enable register (address: 14h) . . . . . . . . . 34 9.3 data ?ow registers . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.3.1 endpoint index register (address: 2ch) . . . . . . . . . . 36 9.3.2 control function register (address: 28h) . . . . . . . . . 37 9.3.3 data port register (address: 20h). . . . . . . . . . . . . . . 38 9.3.4 buffer length register (address: 1ch) . . . . . . . . . . . 39 9.3.5 buffer status register (address: 1eh) . . . . . . . . . . . . 40 9.3.6 endpoint maxpacketsize register (address: 04h) . . 41 9.3.7 endpoint type register (address: 08h) . . . . . . . . . . . 42 9.4 dma registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.4.1 dma command register (address: 30h) . . . . . . . . . 44 9.4.2 dma transfer counter register (address: 34h) . . . . 46 9.4.3 dma con?guration register (address: 38h) . . . . . . . 47 9.4.4 dma hardware register (address: 3ch) . . . . . . . . . . 49 9.4.5 task file registers (addresses: 40h to 4fh) . . . . . . . 50 9.4.6 dma interrupt reason register (address: 50h). . . . . 53 9.4.7 dma interrupt enable register (address: 54h) . . . . . 55 9.4.8 dma endpoint register (address: 58h) . . . . . . . . . . . 56 9.4.9 dma strobe timing register (address: 60h) . . . . . . . 56 9.4.10 dma burst counter register (address: 64h) . . . . . . . 57 9.5 general registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.5.1 interrupt register (address: 18h) . . . . . . . . . . . . . . . . 57 9.5.2 chip id register (address: 70h) . . . . . . . . . . . . . . . . 59 9.5.3 frame number register (address: 74h). . . . . . . . . . . 60 9.5.4 scratch register (address: 78h) . . . . . . . . . . . . . . . . 60 9.5.5 unlock device register (address: 7ch) . . . . . . . . . . . 61 9.5.6 test mode register (address: 84h) . . . . . . . . . . . . . . 62 10 limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11 recommended operating conditions . . . . . . . . . . . . 63 12 static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 63 13 dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . 65 13.1 register access timing . . . . . . . . . . . . . . . . . . . . . . . 67 13.1.1 generic processor mode . . . . . . . . . . . . . . . . . . . . . 67 13.1.2 split bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 13.2 dma timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 13.2.1 pio mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 13.2.2 gdma slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . 77 13.2.3 mdma mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 14 application information . . . . . . . . . . . . . . . . . . . . . . . 80 15 test information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 16 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 17 soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 17.1 introduction to soldering surface mount packages . . 82 17.2 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 17.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 17.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 17.5 package related soldering information . . . . . . . . . . . 83 18 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 19 data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 20 de?nitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 21 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 22 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

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